127 lines
2.1 KiB
Plaintext
127 lines
2.1 KiB
Plaintext
;*****************************
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;*** Fast Lib Replacements ***
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;*****************************
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include gtereg.h
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opt at+
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section .text
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;******************************************************************************
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; New Mem copy
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; a0 = destination address
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; a1 = source address
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; a2 = length
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;
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global MCmemcpy
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MCmemcpy:
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move t0,a0 ; t0 = return address
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; addu t0,a1,a2 ; not sure about this t0 = return address
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beq zero,a2,@all_done ; zero length
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nop
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andi v0,a2,$fffffffc ; check size
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beq zero,v0,@mem_store_bytes ; check for less than 4
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move v1,a2 ; if memcpy less than 4, need size set up
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andi v0,a2,$3
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subu a2,a2,v0 ; make an even four
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move v1,v0
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andi v0,a1,$3 ; check source address non aligned
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beq zero,v0,@source_align
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andi v0,a0,$3 ; check dest address non aligned
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beq zero,v0,@dest_align
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;
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; must not be aligned
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;
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@mem_store_byte_words:
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lwr v0,0(a1)
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lwl v0,3(a1)
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addiu a1,a1,$4
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swr v0,0(a0)
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swl v0,3(a0)
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addiu a2,-$4
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bne zero,a2,@mem_store_byte_words
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addiu a0,a0,$4
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@mem_store_bytes:
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lb v0,0(a1)
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addiu a1,a1,$1
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sb v0,0(a0)
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addiu v1,v1,-$1
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bne zero,v1,@mem_store_bytes
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addiu a0,a0,$1
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@all_done: move v0,t0
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jr ra
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nop
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@source_align: andi v0,a0,$3 ; check dest address aligned
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beq zero,v0,@mem_store_words
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nop
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;
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; source align dest disp
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;
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@mem_store_half2:
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lw v0,0(a1)
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addiu a1,a1,$4
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swr v0,0(a0)
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swl v0,3(a0)
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addiu a2,a2,-$4
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bne zero,a2,@mem_store_half2
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addiu a0,a0,$4
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bne zero,v1,@mem_store_bytes
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move v0,t0
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jr ra
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nop
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@dest_align: andi v0,a1,$3 ; check source address aligned
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beq zero,v0,@mem_store_words
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;
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; source disp 2 dest align
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;
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@mem_store_half1:
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lwr v0,0(a1) ; get first bit
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lwl v0,3(a1) ; get second bit
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addiu a1,a1,$4
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addiu a2,a2,-$4
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sw v0,0(a0)
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bne zero,a2,@mem_store_half1
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addiu a0,a0,$4
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bne zero,v1,@mem_store_bytes
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move v0,t0
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jr ra
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nop
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;
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; source and dest align
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;
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@mem_store_words:
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lw v0,0(a1) ; get first word
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addiu a1,a1,$4
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sw v0,0(a0) ; store it
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addiu a2,a2,-$4
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bne zero,a2,@mem_store_words
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addi a0,a0,$4
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bne zero,v1,@mem_store_bytes
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move v0,t0
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jr ra
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nop
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