245 lines
7.8 KiB
C
245 lines
7.8 KiB
C
/*
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* File:r3000.h
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*/
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/*
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* $PSLibId: Run-time Library Release 4.7$
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*/
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#ifndef _R3000_H
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#define _R3000_H
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/*
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* Segment base addresses and sizes
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*/
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#define K0BASE 0x80000000
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#define K0SIZE 0x20000000
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#define K1BASE 0xA0000000
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#define K1SIZE 0x20000000
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#define K2BASE 0xC0000000
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#define K2SIZE 0x20000000
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/*
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* Exception vectors
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*/
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#define UT_VEC K0BASE /* utlbmiss vector */
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#define E_VEC (K0BASE+0x80) /* exception vector */
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#define R_VEC (K1BASE+0x1fc00000) /* reset vector */
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/*
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* Address conversion macros
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*/
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#define K0_TO_K1(x) ((unsigned)(x)|0xA0000000) /* kseg0 to kseg1 */
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#define K1_TO_K0(x) ((unsigned)(x)&0x9FFFFFFF) /* kseg1 to kseg0 */
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#define K0_TO_PHYS(x) ((unsigned)(x)&0x1FFFFFFF) /* kseg0 to physical */
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#define K1_TO_PHYS(x) ((unsigned)(x)&0x1FFFFFFF) /* kseg1 to physical */
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#define PHYS_TO_K0(x) ((unsigned)(x)|0x80000000) /* physical to kseg0 */
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#define PHYS_TO_K1(x) ((unsigned)(x)|0xA0000000) /* physical to kseg1 */
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/*
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* Address predicates
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*/
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#define IS_KSEG0(x) ((unsigned)(x) >= K0BASE && (unsigned)(x) < K1BASE)
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#define IS_KSEG1(x) ((unsigned)(x) >= K1BASE && (unsigned)(x) < K2BASE)
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#define IS_KSEG2(x) ((unsigned)(x) >= K2BASE && (unsigned)(x) < KPTEBASE)
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#define IS_KPTESEG(x) ((unsigned)(x) >= KPTEBASE)
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#define IS_KUSEG(x) ((unsigned)(x) < K0BASE)
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/*
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* Cache size constants
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*/
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#define MINCACHE +(4*1024) /* leading plus for mas's benefit */
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#define MAXCACHE +(64*1024) /* leading plus for mas's benefit */
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/*
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* Status register
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*/
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#define SR_CUMASK 0xf0000000 /* coproc usable bits */
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#define SR_CU3 0x80000000 /* Coprocessor 3 usable */
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#define SR_CU2 0x40000000 /* Coprocessor 2 usable */
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#define SR_CU1 0x20000000 /* Coprocessor 1 usable */
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#define SR_CU0 0x10000000 /* Coprocessor 0 usable */
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#define SR_BEV 0x00400000 /* use boot exception vectors */
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/* Cache control bits */
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#define SR_TS 0x00200000 /* TLB shutdown */
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#define SR_PE 0x00100000 /* cache parity error */
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#define SR_CM 0x00080000 /* cache miss */
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#define SR_PZ 0x00040000 /* cache parity zero */
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#define SR_SWC 0x00020000 /* swap cache */
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#define SR_ISC 0x00010000 /* Isolate data cache */
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#define SR_MM_MODE 0x00010000 /* lwl/swl/etc become scache/etc */
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#define lcache lwl
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#define scache swl
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#define flush lwr $0,
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#define inval swr $0,
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/*
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* Interrupt enable bits
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* (NOTE: bits set to 1 enable the corresponding level interrupt)
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*/
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#define SR_IMASK 0x0000ff00 /* Interrupt mask */
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#define SR_IMASK8 0x00000000 /* mask level 8 */
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#define SR_IMASK7 0x00008000 /* mask level 7 */
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#define SR_IMASK6 0x0000c000 /* mask level 6 */
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#define SR_IMASK5 0x0000e000 /* mask level 5 */
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#define SR_IMASK4 0x0000f000 /* mask level 4 */
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#define SR_IMASK3 0x0000f800 /* mask level 3 */
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#define SR_IMASK2 0x0000fc00 /* mask level 2 */
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#define SR_IMASK1 0x0000fe00 /* mask level 1 */
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#define SR_IMASK0 0x0000ff00 /* mask level 0 */
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#define SR_IBIT8 0x00008000 /* bit level 8 */
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#define SR_IBIT7 0x00004000 /* bit level 7 */
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#define SR_IBIT6 0x00002000 /* bit level 6 */
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#define SR_IBIT5 0x00001000 /* bit level 5 */
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#define SR_IBIT4 0x00000800 /* bit level 4 */
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#define SR_IBIT3 0x00000400 /* bit level 3 */
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#define SR_IBIT2 0x00000200 /* bit level 2 */
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#define SR_IBIT1 0x00000100 /* bit level 1 */
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#define SR_KUO 0x00000020 /* old kernel/user, 0 => k, 1 => u */
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#define SR_IEO 0x00000010 /* old interrupt enable, 1 => enable */
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#define SR_KUP 0x00000008 /* prev kernel/user, 0 => k, 1 => u */
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#define SR_IEP 0x00000004 /* prev interrupt enable, 1 => enable */
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#define SR_KUC 0x00000002 /* cur kernel/user, 0 => k, 1 => u */
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#define SR_IEC 0x00000001 /* cur interrupt enable, 1 => enable */
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#define SR_IMASKSHIFT 8
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#define SR_FMT "\20\40BD\26TS\25PE\24CM\23PZ\22SwC\21IsC\20IM7\17IM6\16IM5\15IM4\14IM3\13IM2\12IM1\11IM0\6KUo\5IEo\4KUp\3IEp\2KUc\1IEc"
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/*
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* Cause Register
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*/
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#define CAUSE_BD 0x80000000 /* Branch delay slot */
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#define CAUSE_CEMASK 0x30000000 /* coprocessor error */
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#define CAUSE_CESHIFT 28
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/* Interrupt pending bits */
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#define CAUSE_IP8 0x00008000 /* External level 8 pending */
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#define CAUSE_IP7 0x00004000 /* External level 7 pending */
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#define CAUSE_IP6 0x00002000 /* External level 6 pending */
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#define CAUSE_IP5 0x00001000 /* External level 5 pending */
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#define CAUSE_IP4 0x00000800 /* External level 4 pending */
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#define CAUSE_IP3 0x00000400 /* External level 3 pending */
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#define CAUSE_SW2 0x00000200 /* Software level 2 pending */
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#define CAUSE_SW1 0x00000100 /* Software level 1 pending */
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#define CAUSE_IPMASK 0x0000FF00 /* Pending interrupt mask */
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#define CAUSE_IPSHIFT 8
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#define CAUSE_EXCMASK 0x0000003C /* Cause code bits */
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#define CAUSE_EXCSHIFT 2
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#define CAUSE_FMT "\20\40BD\36CE1\35CE0\20IP8\17IP7\16IP6\15IP5\14IP4\13IP3\12SW2\11SW1\1INT"
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/* Cause register exception codes */
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#define EXC_CODE(x) ((x)<<2)
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/* Hardware exception codes */
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#define EXC_INT EXC_CODE(0) /* interrupt */
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#define EXC_MOD EXC_CODE(1) /* TLB mod */
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#define EXC_RMISS EXC_CODE(2) /* Read TLB Miss */
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#define EXC_WMISS EXC_CODE(3) /* Write TLB Miss */
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#define EXC_RADE EXC_CODE(4) /* Read Address Error */
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#define EXC_WADE EXC_CODE(5) /* Write Address Error */
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#define EXC_IBE EXC_CODE(6) /* Instruction Bus Error */
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#define EXC_DBE EXC_CODE(7) /* Data Bus Error */
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#define EXC_SYSCALL EXC_CODE(8) /* SYSCALL */
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#define EXC_BREAK EXC_CODE(9) /* BREAKpoint */
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#define EXC_II EXC_CODE(10) /* Illegal Instruction */
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#define EXC_CPU EXC_CODE(11) /* CoProcessor Unusable */
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#define EXC_OV EXC_CODE(12) /* OVerflow */
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/* software exception codes */
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#define SEXC_SEGV EXC_CODE(16) /* Software detected seg viol */
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#define SEXC_RESCHED EXC_CODE(17) /* resched request */
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#define SEXC_PAGEIN EXC_CODE(18) /* page-in request */
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#define SEXC_CPU EXC_CODE(19) /* coprocessor unusable */
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/*
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* Coprocessor 0 registers
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*/
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#define C0_INX $0 /* tlb index */
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#define C0_RAND $1 /* tlb random */
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#define C0_TLBLO $2 /* tlb entry low */
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#define C0_CTXT $4 /* tlb context */
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#define C0_PIDMASK $6 /* Mips2 */
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#define C0_BADVADDR $8 /* bad virtual address */
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#define C0_TLBHI $10 /* tlb entry hi */
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#define C0_PID $10 /* Mips2 */
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#define C0_SR $12 /* status register */
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#define C0_CAUSE $13 /* exception cause */
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#define C0_EPC $14 /* exception pc */
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#define C0_PRID $15 /* revision identifier */
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#define C0_ERREG $16 /* Mips2 */
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/*
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* Coprocessor 0 operations
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*/
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#define C0_READI 0x1 /* read ITLB entry addressed by C0_INDEX */
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#define C0_WRITEI 0x2 /* write ITLB entry addressed by C0_INDEX */
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#define C0_WRITER 0x6 /* write ITLB entry addressed by C0_RAND */
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#define C0_PROBE 0x8 /* probe for ITLB entry addressed by TLBHI */
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#define C0_RFE 0x10 /* restore for exception */
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/*
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* Flags for the nofault handler. 0 means no fault is expected.
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*/
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#define NF_BADADDR 1 /* badaddr, wbadaddr */
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#define NF_COPYIO 2 /* copyin, copyout */
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#define NF_ADDUPC 3 /* addupc */
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#define NF_FSUMEM 4 /* fubyte, subyte, fuword, suword */
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#define NF_USERACC 5 /* useracc */
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#define NF_SOFTFP 6 /* softfp */
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#define NF_REVID 7 /* revision ids */
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#define NF_NENTRIES 8
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/*
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* TLB size constants
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*/
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#define TLBWIREDBASE 0 /* WAG for now */
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#define NWIREDENTRIES 8 /* WAG for now */
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#define TLBRANDOMBASE NWIREDENTRIES
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#define NRANDOMENTRIES (NTLBENTRIES-NWIREDENTRIES)
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#define NTLBENTRIES 64 /* WAG for now */
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#define TLBRAND_RANDMASK 0x00003f00
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#define TLBRAND_RANDSHIFT 8
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/*
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* Chip interrupt vector
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*/
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#define NC0VECS 8
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#ifndef LOCORE
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#ifdef KERNEL
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#if defined(_LANGUAGE_C_PLUS_PLUS)||defined(__cplusplus)||defined(c_plusplus)
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extern "C" {
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#endif
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extern int (*c0vec_tbl[])();
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#if defined(_LANGUAGE_C_PLUS_PLUS)||defined(__cplusplus)||defined(c_plusplus)
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}
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#endif
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#endif
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#endif /* !LOCORE */
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#define BRK_KERNEL 0xf1
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#define EXCEPT_NORM 1
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#define EXCEPT_UTLB 2
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#define EXCEPT_BRKPT 3
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#define EXCEPT_DB 4
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#define EXCEPT_GDB 4
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#define EXCEPT_INT 9
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#define EXCEPT_ELSE 0xff
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#endif /* _R3000_H */
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