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llvm-mirror/lib/Target/VE/VEISelLowering.h

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[VE] Minimal codegen for empty functions Summary: This patch implements minimal VE code generation for empty function bodies (no args, no value return). Contents * empty function code generation test. * Minimal function prologue & epilogue emission * Instruction formats and instruction definitions as far as required for the empty function prologue & epilogue. * I64 register class definitions. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D72598
2020-01-14 09:58:39 +01:00
//===-- VEISelLowering.h - VE DAG Lowering Interface ------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file defines the interfaces that VE uses to lower LLVM code into a
// selection DAG.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_VE_VEISELLOWERING_H
#define LLVM_LIB_TARGET_VE_VEISELLOWERING_H
#include "VE.h"
#include "llvm/CodeGen/TargetLowering.h"
namespace llvm {
class VESubtarget;
namespace VEISD {
enum NodeType : unsigned {
FIRST_NUMBER = ISD::BUILTIN_OP_END,
[VE] global variable isel patterns Summary: Asm expr fixups, isel patterns and tests for global variables addresses. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D73355
2020-01-24 17:33:57 +01:00
[VE] Support SJLJ exception related instructions Support EH_SJLJ_LONGJMP, EH_SJLJ_SETJMP, and EH_SJLJ_SETUP_DISPATCH for SjLj exception handling. NC++ uses SjLj exception handling, so implement it first. Add regression tests also. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D94071
2020-12-15 13:50:17 +01:00
CALL, // A call instruction.
EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
GETFUNPLT, // Load function address through %plt insturction.
GETTLSADDR, // Load address for TLS access.
GETSTACKTOP, // Retrieve address of stack top (first address of
// locals and temporaries).
GLOBAL_BASE_REG, // Global base reg for PIC.
Hi, // Hi/Lo operations, typically on a global address.
Lo, // Hi/Lo operations, typically on a global address.
MEMBARRIER, // Compiler barrier only; generate a no-op.
RET_FLAG, // Return with a flag operand.
TS1AM, // A TS1AM instruction used for 1/2 bytes swap.
VEC_BROADCAST, // A vector broadcast instruction.
// 0: scalar value, 1: VL
[VE] VE Vector Predicated SDNode, vector add isel and tests VE Vector Predicated (VVP) SDNodes form an intermediate layer between VE vector instructions and the initial SDNodes. We introduce 'vvp_add' with isel and tests as the first of these VVP nodes. VVP nodes have a mask and explicit vector length operand, which we will make proper use of later. Reviewed By: kaz7 Differential Revision: https://reviews.llvm.org/D91802
2020-11-23 15:33:10 +01:00
[VE] Support atomic exchange instructions Support atomic exchange and atomic compare and exchange instructions. Change CAS and TS1AM instructions for ISel patterns. Add selectADDRzi pattern for them. Add TS1AM pseudo instruction also for better ISel. Add shouldExpandAtomicRMWInIR() function to expand all atomicrmw instructions except atomicrmw xchg. Add custom lower for i8/i16 atomicrmw xchg. Modify replaceFI to support CAS/TS1AM instructions which use "reg+disp" operands instead of "reg+imm+disp" operands. And, add several regression tests to check the correctness. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D93161
2020-12-12 04:27:32 +01:00
// VVP_* nodes.
[VE] VE Vector Predicated SDNode, vector add isel and tests VE Vector Predicated (VVP) SDNodes form an intermediate layer between VE vector instructions and the initial SDNodes. We introduce 'vvp_add' with isel and tests as the first of these VVP nodes. VVP nodes have a mask and explicit vector length operand, which we will make proper use of later. Reviewed By: kaz7 Differential Revision: https://reviews.llvm.org/D91802
2020-11-23 15:33:10 +01:00
#define ADD_VVP_OP(VVP_NAME, ...) VVP_NAME,
#include "VVPNodes.def"
[VE] Minimal codegen for empty functions Summary: This patch implements minimal VE code generation for empty function bodies (no args, no value return). Contents * empty function code generation test. * Minimal function prologue & epilogue emission * Instruction formats and instruction definitions as far as required for the empty function prologue & epilogue. * I64 register class definitions. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D72598
2020-01-14 09:58:39 +01:00
};
}
class VETargetLowering : public TargetLowering {
const VESubtarget *Subtarget;
[VE][NFC] Split up lowering init Split up the monolithic VETargetLowering ctor into three initialization phases: 1. initRegisterClasses() 2. initSPUActions() 3. // TODO initVPUActions() Reviewed By: kaz7 Differential Revision: https://reviews.llvm.org/D90463
2020-10-30 16:14:42 +01:00
void initRegisterClasses();
void initSPUActions();
[VE] Add +vpu attribute `+vpu` controls whether VEISelLowering adds any vregs. This defaults to `-vpu` to have scalar code generation out of the box. We bring up vector isel under the `+vpu` flag. Once vector isel is stable we switch to `+vpu` and advertise vregs and vops in TTI. Reviewed By: kaz7 Differential Revision: https://reviews.llvm.org/D90465
2020-11-04 12:41:11 +01:00
void initVPUActions();
[VE][NFC] Split up lowering init Split up the monolithic VETargetLowering ctor into three initialization phases: 1. initRegisterClasses() 2. initSPUActions() 3. // TODO initVPUActions() Reviewed By: kaz7 Differential Revision: https://reviews.llvm.org/D90463
2020-10-30 16:14:42 +01:00
[VE] Minimal codegen for empty functions Summary: This patch implements minimal VE code generation for empty function bodies (no args, no value return). Contents * empty function code generation test. * Minimal function prologue & epilogue emission * Instruction formats and instruction definitions as far as required for the empty function prologue & epilogue. * I64 register class definitions. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D72598
2020-01-14 09:58:39 +01:00
public:
VETargetLowering(const TargetMachine &TM, const VESubtarget &STI);
const char *getTargetNodeName(unsigned Opcode) const override;
[VE] i<N> and fp32/64 arguments, return values and constants Summary: Support for i<N> and fp32/64 arguments (in register), return values and constants along with tests. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D73092
2020-01-22 09:17:36 +01:00
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
return MVT::i32;
}
[VE] Minimal codegen for empty functions Summary: This patch implements minimal VE code generation for empty function bodies (no args, no value return). Contents * empty function code generation test. * Minimal function prologue & epilogue emission * Instruction formats and instruction definitions as far as required for the empty function prologue & epilogue. * I64 register class definitions. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D72598
2020-01-14 09:58:39 +01:00
Register getRegisterByName(const char *RegName, LLT VT,
const MachineFunction &MF) const override;
/// getSetCCResultType - Return the ISD::SETCC ValueType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
EVT VT) const override;
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
const SDLoc &dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const override;
[VE] call isel with stack passing Summary: Function calls and stack-passing of function arguments. Custom lowering, isel patterns and tests. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D73461
2020-01-28 09:55:56 +01:00
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
SmallVectorImpl<SDValue> &InVals) const override;
[VE] Minimal codegen for empty functions Summary: This patch implements minimal VE code generation for empty function bodies (no args, no value return). Contents * empty function code generation test. * Minimal function prologue & epilogue emission * Instruction formats and instruction definitions as far as required for the empty function prologue & epilogue. * I64 register class definitions. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D72598
2020-01-14 09:58:39 +01:00
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
LLVMContext &Context) const override;
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
SelectionDAG &DAG) const override;
[VE] i<N> and fp32/64 arguments, return values and constants Summary: Support for i<N> and fp32/64 arguments (in register), return values and constants along with tests. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D73092
2020-01-22 09:17:36 +01:00
[VE] Support atomic load Support atomic load instruction and add a regression test. VE uses release consitency, so need to insert fence around atomic instructions. This patch enable AtomicExpandPass and use emitLeadingFence and emitTrailingFence mechanism for such purpose. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D90135
2020-10-23 15:10:34 +02:00
/// Helper functions for atomic operations.
bool shouldInsertFencesForAtomic(const Instruction *I) const override {
// VE uses release consistency, so need fence for each atomics.
return true;
}
[VE][NFC] IRBuilder<> -> IRBuilderBase VE's TTI broke with the switch from IRBuilder<> to IRBuilderBase. Following that change to compile again.
2021-06-08 13:55:21 +02:00
Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst,
[VE] Support atomic load Support atomic load instruction and add a regression test. VE uses release consitency, so need to insert fence around atomic instructions. This patch enable AtomicExpandPass and use emitLeadingFence and emitTrailingFence mechanism for such purpose. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D90135
2020-10-23 15:10:34 +02:00
AtomicOrdering Ord) const override;
[VE][NFC] IRBuilder<> -> IRBuilderBase VE's TTI broke with the switch from IRBuilder<> to IRBuilderBase. Following that change to compile again.
2021-06-08 13:55:21 +02:00
Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst,
[VE] Support atomic load Support atomic load instruction and add a regression test. VE uses release consitency, so need to insert fence around atomic instructions. This patch enable AtomicExpandPass and use emitLeadingFence and emitTrailingFence mechanism for such purpose. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D90135
2020-10-23 15:10:34 +02:00
AtomicOrdering Ord) const override;
[VE] Support atomic exchange instructions Support atomic exchange and atomic compare and exchange instructions. Change CAS and TS1AM instructions for ISel patterns. Add selectADDRzi pattern for them. Add TS1AM pseudo instruction also for better ISel. Add shouldExpandAtomicRMWInIR() function to expand all atomicrmw instructions except atomicrmw xchg. Add custom lower for i8/i16 atomicrmw xchg. Modify replaceFI to support CAS/TS1AM instructions which use "reg+disp" operands instead of "reg+imm+disp" operands. And, add several regression tests to check the correctness. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D93161
2020-12-12 04:27:32 +01:00
TargetLoweringBase::AtomicExpansionKind
shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
[VE] Set getExtendForAtomicOps to ISD::ANY_EXTEND The implementation of subword atomics does not actually guarantee the result is zero-extended, which now caused failures after https://reviews.llvm.org/D101342 was landed. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D106225
2021-07-13 22:01:10 +02:00
ISD::NodeType getExtendForAtomicOps() const override {
return ISD::ANY_EXTEND;
}
[VE] Support atomic load Support atomic load instruction and add a regression test. VE uses release consitency, so need to insert fence around atomic instructions. This patch enable AtomicExpandPass and use emitLeadingFence and emitTrailingFence mechanism for such purpose. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D90135
2020-10-23 15:10:34 +02:00
[VE] global variable isel patterns Summary: Asm expr fixups, isel patterns and tests for global variables addresses. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D73355
2020-01-24 17:33:57 +01:00
/// Custom Lower {
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
[VE] Implement JumpTable Implement JumpTable to make BRIND work on VE. Update an existing br_jt regression test also. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D91582
2020-11-17 14:38:49 +01:00
unsigned getJumpTableEncoding() const override;
const MCExpr *LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
const MachineBasicBlock *MBB,
unsigned Uid,
MCContext &Ctx) const override;
SDValue getPICJumpTableRelocBase(SDValue Table,
SelectionDAG &DAG) const override;
// VE doesn't need getPICJumpTableRelocBaseExpr since it is used for only
// EK_LabelDifference32.
[VE] global variable isel patterns Summary: Asm expr fixups, isel patterns and tests for global variables addresses. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D73355
2020-01-24 17:33:57 +01:00
[VE] Support atomic fence Support atomic fence instruction and add a regression test. Add MEMBARRIER pseudo insturction also to use it as a barrier against to the compiler optimizations. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D90112
2020-10-25 03:11:49 +01:00
SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
[VE] Support atomic exchange instructions Support atomic exchange and atomic compare and exchange instructions. Change CAS and TS1AM instructions for ISel patterns. Add selectADDRzi pattern for them. Add TS1AM pseudo instruction also for better ISel. Add shouldExpandAtomicRMWInIR() function to expand all atomicrmw instructions except atomicrmw xchg. Add custom lower for i8/i16 atomicrmw xchg. Modify replaceFI to support CAS/TS1AM instructions which use "reg+disp" operands instead of "reg+imm+disp" operands. And, add several regression tests to check the correctness. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D93161
2020-12-12 04:27:32 +01:00
SDValue lowerATOMIC_SWAP(SDValue Op, SelectionDAG &DAG) const;
[VE] Modify ISelLoweirng following clang-tidy Modify case style of function names following clang-tidy. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D86076
2020-08-17 16:02:24 +02:00
SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
[VE] Support f128 Support f128 using VE instructions. Update regression tests. I've noticed there is no load or store i128 test, so I add them too. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D86035
2020-06-27 12:08:09 +02:00
SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
[VE] Modify ISelLoweirng following clang-tidy Modify case style of function names following clang-tidy. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D86076
2020-08-17 16:02:24 +02:00
SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
[VE] Support SJLJ exception related instructions Support EH_SJLJ_LONGJMP, EH_SJLJ_SETJMP, and EH_SJLJ_SETUP_DISPATCH for SjLj exception handling. NC++ uses SjLj exception handling, so implement it first. Add regression tests also. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D94071
2020-12-15 13:50:17 +01:00
SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
[VE] Modify ISelLoweirng following clang-tidy Modify case style of function names following clang-tidy. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D86076
2020-08-17 16:02:24 +02:00
SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
[VE] Support llvm.eh.sjlj.lsda In order to support SJLJ exception, implement llvm.eh.sjlj.lsda first. Add regression test also. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D93811
2020-12-15 13:50:17 +01:00
SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
[VE] Implement JumpTable Implement JumpTable to make BRIND work on VE. Update an existing br_jt regression test also. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D91582
2020-11-17 14:38:49 +01:00
SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
[VE] Support f128 Support f128 using VE instructions. Update regression tests. I've noticed there is no load or store i128 test, so I add them too. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D86035
2020-06-27 12:08:09 +02:00
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
[VE] Modify ISelLoweirng following clang-tidy Modify case style of function names following clang-tidy. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D86076
2020-08-17 16:02:24 +02:00
SDValue lowerToTLSGeneralDynamicModel(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
[VE] VEC_BROADCAST, lowering and isel This defines the vec_broadcast SDNode along with lowering and isel code. We also remove unused type mappings for the vector register classes (all vector MVTs that are not used in the ISA go). We will implement support for short vectors later by intercepting nodes with illegal vector EVTs before LLVM has had a chance to widen them. Reviewed By: kaz7 Differential Revision: https://reviews.llvm.org/D91646
2020-11-19 09:44:48 +01:00
SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
[VE] Extract & insert vector element isel Isel and tests for extract_vector_elt and insert_vector_elt. Reviewed By: kaz7 Differential Revision: https://reviews.llvm.org/D93687
2021-01-08 11:35:58 +01:00
SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
[VE] global variable isel patterns Summary: Asm expr fixups, isel patterns and tests for global variables addresses. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D73355
2020-01-24 17:33:57 +01:00
/// } Custom Lower
[VE] Support atomic exchange instructions Support atomic exchange and atomic compare and exchange instructions. Change CAS and TS1AM instructions for ISel patterns. Add selectADDRzi pattern for them. Add TS1AM pseudo instruction also for better ISel. Add shouldExpandAtomicRMWInIR() function to expand all atomicrmw instructions except atomicrmw xchg. Add custom lower for i8/i16 atomicrmw xchg. Modify replaceFI to support CAS/TS1AM instructions which use "reg+disp" operands instead of "reg+imm+disp" operands. And, add several regression tests to check the correctness. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D93161
2020-12-12 04:27:32 +01:00
/// Replace the results of node with an illegal result
/// type with new values built out of custom code.
///
void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG) const override;
[VE] Support SJLJ exception related instructions Support EH_SJLJ_LONGJMP, EH_SJLJ_SETJMP, and EH_SJLJ_SETUP_DISPATCH for SjLj exception handling. NC++ uses SjLj exception handling, so implement it first. Add regression tests also. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D94071
2020-12-15 13:50:17 +01:00
/// Custom Inserter {
MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr &MI,
MachineBasicBlock *MBB) const override;
MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI,
MachineBasicBlock *MBB) const;
MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI,
MachineBasicBlock *MBB) const;
MachineBasicBlock *emitSjLjDispatchBlock(MachineInstr &MI,
MachineBasicBlock *BB) const;
void setupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
MachineBasicBlock *DispatchBB, int FI,
int Offset) const;
// Setup basic block address.
Register prepareMBB(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
MachineBasicBlock *TargetBB, const DebugLoc &DL) const;
// Prepare function/variable address.
Register prepareSymbol(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
StringRef Symbol, const DebugLoc &DL, bool IsLocal,
bool IsCall) const;
/// } Custom Inserter
[VE] VE Vector Predicated SDNode, vector add isel and tests VE Vector Predicated (VVP) SDNodes form an intermediate layer between VE vector instructions and the initial SDNodes. We introduce 'vvp_add' with isel and tests as the first of these VVP nodes. VVP nodes have a mask and explicit vector length operand, which we will make proper use of later. Reviewed By: kaz7 Differential Revision: https://reviews.llvm.org/D91802
2020-11-23 15:33:10 +01:00
/// VVP Lowering {
SDValue lowerToVVP(SDValue Op, SelectionDAG &DAG) const;
/// } VVPLowering
[VE] Optimize trunc related instructions Change to not generate truncate instructions if all use of a truncate operation don't care about higher bits. For example, an i32 add instruction doesn't care about higher 32 bits in 64 bit registers. Updates regression tests also. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D85418
2020-08-04 09:41:12 +02:00
/// Custom DAGCombine {
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const;
/// } Custom DAGCombine
[VE] global variable isel patterns Summary: Asm expr fixups, isel patterns and tests for global variables addresses. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D73355
2020-01-24 17:33:57 +01:00
SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
SelectionDAG &DAG) const;
SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const;
[VE] Support f128 Support f128 using VE instructions. Update regression tests. I've noticed there is no load or store i128 test, so I add them too. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D86035
2020-06-27 12:08:09 +02:00
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
[VE] i<N> and fp32/64 arguments, return values and constants Summary: Support for i<N> and fp32/64 arguments (in register), return values and constants along with tests. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D73092
2020-01-22 09:17:36 +01:00
bool isFPImmLegal(const APFloat &Imm, EVT VT,
bool ForCodeSize) const override;
[VE] enable unaligned load/store isel Summary: Enable unaligned load/store isel for iN and fp32/64 and tests. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D73448
2020-01-28 09:52:53 +01:00
/// Returns true if the target allows unaligned memory accesses of the
/// specified type.
[VE] Fix allowsMisalignedMemoryAccesses after D96097
2021-02-05 05:46:18 +01:00
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align A,
[VE] enable unaligned load/store isel Summary: Enable unaligned load/store isel for iN and fp32/64 and tests. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D73448
2020-01-28 09:52:53 +01:00
MachineMemOperand::Flags Flags,
bool *Fast) const override;
[VE] udiv/sdiv/urem/srem/mul isel patterns Summary: udiv/sdiv/urem/srem/mul integer isel patterns and tests. Pretend for now that integer division were always cheap in HW. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D73623
2020-01-29 15:59:29 +01:00
[VE] Support inline assembly Support inline assembly with scalar registers. Add a regression test also. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D91119
2020-11-10 05:42:24 +01:00
/// Inline Assembly {
[VE] Support inline assembly with vector regsiters Support inline assembly with vector registers. Add a regression test also. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D91146
2020-11-10 05:42:24 +01:00
ConstraintType getConstraintType(StringRef Constraint) const override;
[VE] Support inline assembly Support inline assembly with scalar registers. Add a regression test also. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D91119
2020-11-10 05:42:24 +01:00
std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint, MVT VT) const override;
/// } Inline Assembly
[VE] Update bit operations Change bitreverse/bswap/ctlz/ctpop/cttz regression tests to support i128 and signext/zeroext i32 types. This patch also change the way to support i32 types using 64 bits VE instructions. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D85712
2020-08-10 10:16:57 +02:00
/// Target Optimization {
[VE] Change threshold for jump table generation Implement getMinimumJumpTableEntries() to specify threshold for jump table genaration. We use 8 for the case of PIC mode to relieve the impact of PIC calculation required to implement PIC mode jump table. Update jump table regression test also. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D91785
2020-11-19 13:31:21 +01:00
// Return lower limit for number of blocks in a jump table.
unsigned getMinimumJumpTableEntries() const override;
[VE] Update bit operations Change bitreverse/bswap/ctlz/ctpop/cttz regression tests to support i128 and signext/zeroext i32 types. This patch also change the way to support i32 types using 64 bits VE instructions. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D85712
2020-08-10 10:16:57 +02:00
// SX-Aurora VE's s/udiv is 5-9 times slower than multiply.
bool isIntDivCheap(EVT, AttributeList) const override { return false; }
// VE doesn't have rem.
bool hasStandaloneRem(EVT) const override { return false; }
// VE LDZ instruction returns 64 if the input is zero.
bool isCheapToSpeculateCtlz() const override { return true; }
// VE LDZ instruction is fast.
bool isCtlzFast() const override { return true; }
// VE has NND instruction.
[VE] Support lowering to NND instruction Summary: Support NND instruction of Aurora VE. Add hasAndNot function also for optimization. Differential Revision: https://reviews.llvm.org/D81383
2020-06-09 10:17:20 +02:00
bool hasAndNot(SDValue Y) const override;
[VE] Update bit operations Change bitreverse/bswap/ctlz/ctpop/cttz regression tests to support i128 and signext/zeroext i32 types. This patch also change the way to support i32 types using 64 bits VE instructions. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D85712
2020-08-10 10:16:57 +02:00
/// } Target Optimization
[VE] Minimal codegen for empty functions Summary: This patch implements minimal VE code generation for empty function bodies (no args, no value return). Contents * empty function code generation test. * Minimal function prologue & epilogue emission * Instruction formats and instruction definitions as far as required for the empty function prologue & epilogue. * I64 register class definitions. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D72598
2020-01-14 09:58:39 +01:00
};
} // namespace llvm
#endif // VE_ISELLOWERING_H
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