2012-02-18 13:03:15 +01:00
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//===-- X86RegisterInfo.h - X86 Register Information Impl -------*- C++ -*-===//
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2005-04-22 01:38:14 +02:00
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//
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2003-10-21 17:17:13 +02:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 21:36:04 +01:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-04-22 01:38:14 +02:00
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//
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2003-10-21 17:17:13 +02:00
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//===----------------------------------------------------------------------===//
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2002-10-26 00:55:53 +02:00
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//
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2008-02-10 19:45:23 +01:00
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// This file contains the X86 implementation of the TargetRegisterInfo class.
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2002-10-26 00:55:53 +02:00
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//
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//===----------------------------------------------------------------------===//
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2014-08-13 18:26:38 +02:00
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#ifndef LLVM_LIB_TARGET_X86_X86REGISTERINFO_H
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#define LLVM_LIB_TARGET_X86_X86REGISTERINFO_H
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2002-10-26 00:55:53 +02:00
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2008-02-10 19:45:23 +01:00
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#include "llvm/Target/TargetRegisterInfo.h"
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2011-06-27 20:32:37 +02:00
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#define GET_REGINFO_HEADER
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#include "X86GenRegisterInfo.inc"
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2003-11-11 23:41:34 +01:00
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namespace llvm {
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class Triple;
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2014-03-31 08:53:13 +02:00
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class X86RegisterInfo final : public X86GenRegisterInfo {
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private:
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/// Is64Bit - Is the target 64-bits.
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///
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bool Is64Bit;
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2008-03-22 22:04:01 +01:00
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/// IsWin64 - Is the target on of win64 flavours
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///
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bool IsWin64;
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/// SlotSize - Stack slot size in bytes.
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///
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unsigned SlotSize;
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/// StackPtr - X86 physical register used as stack ptr.
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///
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unsigned StackPtr;
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/// FramePtr - X86 physical register used as frame ptr.
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///
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unsigned FramePtr;
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/// BasePtr - X86 physical register used as a base ptr in complex stack
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/// frames. I.e., when we need a 3rd base, not just SP and FP, due to
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/// variable size stack objects.
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unsigned BasePtr;
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public:
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X86RegisterInfo(const Triple &TT);
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2011-05-24 18:57:53 +02:00
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// FIXME: This should be tablegen'd like getDwarfRegNum is
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int getSEHRegNum(unsigned i) const;
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2002-12-28 21:32:54 +01:00
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/// Code Generation virtual methods...
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2012-04-23 23:39:35 +02:00
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///
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bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
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2009-07-18 04:10:10 +02:00
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/// getMatchingSuperRegClass - Return a subclass of the specified register
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/// class A so that each register in it has a sub-register of the
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/// specified sub-register index which is in the specified register class B.
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const TargetRegisterClass *
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getMatchingSuperRegClass(const TargetRegisterClass *A,
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const TargetRegisterClass *B,
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unsigned Idx) const override;
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const TargetRegisterClass *
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getSubClassWithSubReg(const TargetRegisterClass *RC,
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unsigned Idx) const override;
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2015-03-11 00:46:01 +01:00
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const TargetRegisterClass *
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getLargestLegalSuperClass(const TargetRegisterClass *RC,
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const MachineFunction &MF) const override;
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2009-02-06 18:43:24 +01:00
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/// getPointerRegClass - Returns a TargetRegisterClass used for pointer
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/// values.
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const TargetRegisterClass *
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getPointerRegClass(const MachineFunction &MF,
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unsigned Kind = 0) const override;
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2008-10-27 08:14:50 +01:00
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/// getCrossCopyRegClass - Returns a legal register class to copy a register
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/// in the specified class to or from. Returns NULL if it is possible to copy
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/// between a two registers of the specified class.
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const TargetRegisterClass *
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getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
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2015-11-23 23:17:44 +01:00
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/// getGPRsForTailCall - Returns a register class with registers that can be
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/// used in forming tail calls.
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const TargetRegisterClass *
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getGPRsForTailCall(const MachineFunction &MF) const;
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2011-03-07 22:56:36 +01:00
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unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const override;
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2007-01-02 22:33:40 +01:00
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/// getCalleeSavedRegs - Return a null-terminated list of all of the
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2006-05-18 02:12:58 +02:00
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/// callee-save registers on this target.
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const MCPhysReg *
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getCalleeSavedRegs(const MachineFunction* MF) const override;
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const MCPhysReg *
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getCalleeSavedRegsViaCopy(const MachineFunction *MF) const override;
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2015-03-11 23:42:13 +01:00
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const uint32_t *getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID) const override;
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2015-11-06 18:06:38 +01:00
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const uint32_t *getNoPreservedMask() const override;
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2006-05-18 02:12:58 +02:00
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2015-11-12 01:54:04 +01:00
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// Calls involved in thread-local variable lookup save more registers than
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// normal calls, so they need a different mask to represent this.
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const uint32_t *getDarwinTLSCallPreservedMask() const;
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2007-02-19 22:49:54 +01:00
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/// getReservedRegs - Returns a bitset indexed by physical register number
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/// indicating if a register is a special register that has particular uses and
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/// should be considered unavailable at all times, e.g. SP, RA. This is used by
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/// register scavenger to determine what registers are free.
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BitVector getReservedRegs(const MachineFunction &MF) const override;
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2007-02-19 22:49:54 +01:00
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2015-06-12 00:40:04 +02:00
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void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
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2012-07-10 19:45:53 +02:00
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bool hasBasePointer(const MachineFunction &MF) const;
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Targets: commonize some stack realignment code
This patch does the following:
* Fix FIXME on `needsStackRealignment`: it is now shared between multiple targets, implemented in `TargetRegisterInfo`, and isn't `virtual` anymore. This will break out-of-tree targets, silently if they used `virtual` and with a build error if they used `override`.
* Factor out `canRealignStack` as a `virtual` function on `TargetRegisterInfo`, by default only looks for the `no-realign-stack` function attribute.
Multiple targets duplicated the same `needsStackRealignment` code:
- Aarch64.
- ARM.
- Mips almost: had extra `DEBUG` diagnostic, which the default implementation now has.
- PowerPC.
- WebAssembly.
- x86 almost: has an extra `-force-align-stack` option, which the default implementation now has.
The default implementation of `needsStackRealignment` used to just return `false`. My current patch changes the behavior by simply using the above shared behavior. This affects:
- AMDGPU
- BPF
- CppBackend
- MSP430
- NVPTX
- Sparc
- SystemZ
- XCore
- Out-of-tree targets
This is a breaking change! `make check` passes.
The only implementation of the `virtual` function (besides the slight different in x86) was Hexagon (which did `MF.getFrameInfo()->getMaxAlignment() > 8`), and potentially some out-of-tree targets. Hexagon now uses the default implementation.
`needsStackRealignment` was being overwritten in `<Target>GenRegisterInfo.inc`, to return `false` as the default also did. That was odd and is now gone.
Reviewers: sunfish
Subscribers: aemerson, llvm-commits, jfb
Differential Revision: http://reviews.llvm.org/D11160
llvm-svn: 242727
2015-07-21 00:51:32 +02:00
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bool canRealignStack(const MachineFunction &MF) const override;
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2008-04-23 20:15:48 +02:00
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2010-07-20 08:52:21 +02:00
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bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
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int &FrameIdx) const override;
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2009-07-09 08:53:48 +02:00
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2010-08-27 01:32:16 +02:00
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void eliminateFrameIndex(MachineBasicBlock::iterator MI,
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2013-01-31 21:02:54 +01:00
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int SPAdj, unsigned FIOperandNum,
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2014-04-28 06:05:08 +02:00
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RegScavenger *RS = nullptr) const override;
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2002-11-20 19:59:43 +01:00
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2006-03-28 15:48:33 +02:00
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// Debug information queries.
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unsigned getFrameRegister(const MachineFunction &MF) const override;
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unsigned getPtrSizedFrameRegister(const MachineFunction &MF) const;
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unsigned getStackRegister() const { return StackPtr; }
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unsigned getBaseRegister() const { return BasePtr; }
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2010-11-15 01:06:54 +01:00
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// FIXME: Move to FrameInfok
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unsigned getSlotSize() const { return SlotSize; }
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};
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2013-07-24 13:02:47 +02:00
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//get512BitRegister - X86 utility - returns 512-bit super register
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unsigned get512BitSuperRegister(unsigned Reg);
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2015-06-23 11:49:53 +02:00
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} // End llvm namespace
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2003-11-11 23:41:34 +01:00
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2002-10-26 00:55:53 +02:00
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#endif
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