llvm-mirror/test/CodeGen/X86/fp-stack-compare-cmov.ll

; RUN: llc < %s -march=x86 -mcpu=pentiumpro | FileCheck %s
; PR1012

define float @foo(float* %col.2.0) {
; CHECK: fucompi
; CHECK: fcmov
  %tmp = load float, float* %col.2.0
  %tmp16 = fcmp olt float %tmp, 0.000000e+00
  %tmp20 = fsub float -0.000000e+00, %tmp
  %iftmp.2.0 = select i1 %tmp16, float %tmp20, float %tmp
  ret float %iftmp.2.0
}
X86: Don't emit conditional floating point moves on when targeting pre-pentiumpro architectures. * Model FPSW (the FPU status word) as a register. * Add ISel patterns for the FUCOM, FNSTSW and SAHF instructions. During Legalize/Lowering, build a node sequence to transfer the comparison result from FPSW into EFLAGS. If you're wondering about the right-shift: That's an implicit sub-register extraction (%ax -> %ah) which is handled later on by the instruction selector. Fixes PR6679. Patch by Christoph Erhardt! llvm-svn: 155704 2012-04-27 14:07:43 +02:00			`; RUN: llc < %s -march=x86 -mcpu=pentiumpro \| FileCheck %s`
			`; PR1012`

			`define float @foo(float* %col.2.0) {`
			`; CHECK: fucompi`
			`; CHECK: fcmov`
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=\|:\|^)\sload (?:atomic )?(?:volatile )?(.?))(\| addrspace\(\d+\) )\($\| (?:%\|@\|null\|undef\|blockaddress\|getelementptr\|addrspacecast\|bitcast\|inttoptr\|\[\[[a-zA-Z]\|\{\{).$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794 2015-02-27 22:17:42 +01:00			`%tmp = load float, float* %col.2.0`
X86: Don't emit conditional floating point moves on when targeting pre-pentiumpro architectures. * Model FPSW (the FPU status word) as a register. * Add ISel patterns for the FUCOM, FNSTSW and SAHF instructions. During Legalize/Lowering, build a node sequence to transfer the comparison result from FPSW into EFLAGS. If you're wondering about the right-shift: That's an implicit sub-register extraction (%ax -> %ah) which is handled later on by the instruction selector. Fixes PR6679. Patch by Christoph Erhardt! llvm-svn: 155704 2012-04-27 14:07:43 +02:00			`%tmp16 = fcmp olt float %tmp, 0.000000e+00`
			`%tmp20 = fsub float -0.000000e+00, %tmp`
			`%iftmp.2.0 = select i1 %tmp16, float %tmp20, float %tmp`
			`ret float %iftmp.2.0`
			`}`