2016-11-02 00:40:28 +01:00
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//===-- RISCV.td - Describe the RISCV Target Machine -------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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2017-10-19 16:29:03 +02:00
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//===----------------------------------------------------------------------===//
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// RISC-V subtarget features and instruction predicates.
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//===----------------------------------------------------------------------===//
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2016-11-02 00:40:28 +01:00
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2017-11-09 15:46:30 +01:00
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def FeatureStdExtM : SubtargetFeature<"m", "HasStdExtM", "true",
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"'M' (Integer Multiplication and Division)">;
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def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
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AssemblerPredicate<"FeatureStdExtM">;
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2016-11-02 00:40:28 +01:00
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2017-11-09 15:46:30 +01:00
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def Feature64Bit : SubtargetFeature<"64bit", "HasRV64", "true",
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"Implements RV64">;
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def RV64 : HwMode<"+64bit">;
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def RV32 : HwMode<"-64bit">;
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2017-10-19 16:29:03 +02:00
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//===----------------------------------------------------------------------===//
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2017-10-19 23:37:38 +02:00
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// Registers, calling conventions, instruction descriptions.
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2017-10-19 16:29:03 +02:00
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//===----------------------------------------------------------------------===//
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include "RISCVRegisterInfo.td"
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2017-10-19 23:37:38 +02:00
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include "RISCVCallingConv.td"
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2017-10-19 16:29:03 +02:00
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include "RISCVInstrInfo.td"
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2016-11-02 00:40:28 +01:00
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2017-10-19 16:29:03 +02:00
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//===----------------------------------------------------------------------===//
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// RISC-V processors supported.
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//===----------------------------------------------------------------------===//
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2016-11-02 00:40:28 +01:00
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def : ProcessorModel<"generic-rv32", NoSchedModel, []>;
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def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
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2017-10-19 16:29:03 +02:00
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//===----------------------------------------------------------------------===//
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// Define the RISC-V target.
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//===----------------------------------------------------------------------===//
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2017-10-19 23:37:38 +02:00
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def RISCVInstrInfo : InstrInfo {
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2017-11-08 10:26:06 +01:00
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let guessInstructionProperties = 0;
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2017-10-19 23:37:38 +02:00
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}
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2017-10-19 16:29:03 +02:00
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2017-08-08 16:32:35 +02:00
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def RISCVAsmParser : AsmParser {
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let ShouldEmitMatchRegisterAltName = 1;
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}
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2016-11-02 00:40:28 +01:00
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def RISCV : Target {
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let InstructionSet = RISCVInstrInfo;
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2017-08-08 16:32:35 +02:00
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let AssemblyParsers = [RISCVAsmParser];
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2016-11-02 00:40:28 +01:00
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}
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