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llvm-mirror/test/CodeGen/AArch64/arm64-ands-bad-peephole.ll

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ARM & AArch64: make use of common cmpxchg idioms after expansion The C and C++ semantics for compare_exchange require it to return a bool indicating success. This gets mapped to LLVM IR which follows each cmpxchg with an icmp of the value loaded against the desired value. When lowered to ldxr/stxr loops, this extra comparison is redundant: its results are implicit in the control-flow of the function. This commit makes two changes: it replaces that icmp with appropriate PHI nodes, and then makes sure earlyCSE is called after expansion to actually make use of the opportunities revealed. I've also added -{arm,aarch64}-enable-atomic-tidy options, so that existing fragile tests aren't perturbed too much by the change. Many of them either rely on undef/unreachable too pervasively to be restored to something well-defined (particularly while making sure they test the same obscure assert from many years ago), or depend on a particular CFG shape, which is disrupted by SimplifyCFG. rdar://problem/16227836 llvm-svn: 209883
2014-05-30 12:09:59 +02:00
; RUN: llc %s -o - -aarch64-atomic-cfg-tidy=0 | FileCheck %s
[ARM64] Fix the information we give to the peephole optimizer for comparison. ANDS does not use the same encoding scheme as other xxxS instructions (e.g., ADDS). Take that into account to avoid wrong peephole optimization. <rdar://problem/16693089> llvm-svn: 207020
2014-04-23 22:43:38 +02:00
; Check that ANDS (tst) is not merged with ADD when the immediate
; is not 0.
; <rdar://problem/16693089>
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-ios"
; CHECK-LABEL: tst1:
; CHECK: add [[REG:w[0-9]+]], w{{[0-9]+}}, #1
; CHECK: tst [[REG]], #0x1
AArch64 & ARM: remove undefined behaviour from some tests. llvm-svn: 209880
2014-05-30 10:59:55 +02:00
define void @tst1(i1 %tst, i32 %true) {
[ARM64] Fix the information we give to the peephole optimizer for comparison. ANDS does not use the same encoding scheme as other xxxS instructions (e.g., ADDS). Take that into account to avoid wrong peephole optimization. <rdar://problem/16693089> llvm-svn: 207020
2014-04-23 22:43:38 +02:00
entry:
AArch64 & ARM: remove undefined behaviour from some tests. llvm-svn: 209880
2014-05-30 10:59:55 +02:00
br i1 %tst, label %for.end, label %for.body
[ARM64] Fix the information we give to the peephole optimizer for comparison. ANDS does not use the same encoding scheme as other xxxS instructions (e.g., ADDS). Take that into account to avoid wrong peephole optimization. <rdar://problem/16693089> llvm-svn: 207020
2014-04-23 22:43:38 +02:00
for.body: ; preds = %for.body, %entry
%result.09 = phi i32 [ %add2.result.0, %for.body ], [ 1, %entry ]
%i.08 = phi i32 [ %inc, %for.body ], [ 2, %entry ]
%and = and i32 %i.08, 1
%cmp1 = icmp eq i32 %and, 0
AArch64 & ARM: remove undefined behaviour from some tests. llvm-svn: 209880
2014-05-30 10:59:55 +02:00
%add2.result.0 = select i1 %cmp1, i32 %true, i32 %result.09
[ARM64] Fix the information we give to the peephole optimizer for comparison. ANDS does not use the same encoding scheme as other xxxS instructions (e.g., ADDS). Take that into account to avoid wrong peephole optimization. <rdar://problem/16693089> llvm-svn: 207020
2014-04-23 22:43:38 +02:00
%inc = add nsw i32 %i.08, 1
AArch64 & ARM: remove undefined behaviour from some tests. llvm-svn: 209880
2014-05-30 10:59:55 +02:00
%cmp = icmp slt i32 %i.08, %true
[ARM64] Fix the information we give to the peephole optimizer for comparison. ANDS does not use the same encoding scheme as other xxxS instructions (e.g., ADDS). Take that into account to avoid wrong peephole optimization. <rdar://problem/16693089> llvm-svn: 207020
2014-04-23 22:43:38 +02:00
br i1 %cmp, label %for.body, label %for.cond.for.end_crit_edge
for.cond.for.end_crit_edge: ; preds = %for.body
%add2.result.0.lcssa = phi i32 [ %add2.result.0, %for.body ]
br label %for.end
for.end: ; preds = %for.cond.for.end_crit_edge, %entry
ret void
}
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