2018-08-03 00:17:53 +02:00
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; RUN: llc -march=hexagon -mno-pairing -mno-compound -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s
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2018-03-12 15:01:28 +01:00
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; Test that we generate the correct phi names in the epilog when the pipeliner
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; schedules a phi and it's loop definition in different stages, e.g., a phi is
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; scheduled in stage 2, but the loop definition in scheduled in stage 0). The
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; code in generateExistingPhis was generating the wrong name for the last
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; epilog bock.
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; CHECK: endloop0
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; CHECK: sub([[REG:r([0-9]+)]],r{{[0-9]+}}):sat
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; CHECK-NOT: sub([[REG]],r{{[0-9]+}}):sat
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define void @f0() {
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b0:
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br label %b1
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b1: ; preds = %b1, %b0
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br i1 undef, label %b2, label %b1
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b2: ; preds = %b1
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br label %b3
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b3: ; preds = %b3, %b2
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%v0 = phi i32 [ %v8, %b3 ], [ 7, %b2 ]
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%v1 = phi i32 [ %v6, %b3 ], [ undef, %b2 ]
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%v2 = phi i32 [ %v1, %b3 ], [ undef, %b2 ]
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%v3 = getelementptr inbounds [9 x i32], [9 x i32]* undef, i32 0, i32 %v0
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%v4 = add nsw i32 %v0, -2
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%v5 = getelementptr inbounds [9 x i32], [9 x i32]* undef, i32 0, i32 %v4
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%v6 = load i32, i32* %v5, align 4
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%v7 = tail call i32 @llvm.hexagon.A2.subsat(i32 %v2, i32 %v6)
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store i32 %v7, i32* %v3, align 4
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%v8 = add i32 %v0, -1
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%v9 = icmp sgt i32 %v8, 1
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br i1 %v9, label %b3, label %b4
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b4: ; preds = %b3
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unreachable
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.A2.subsat(i32, i32) #0
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attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" }
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