llvm-mirror/test/CodeGen/ARM/fdivs.ll

; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0
; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8
; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9

define float @test(float %a, float %b) {
entry:
	%0 = fdiv float %a, %b
	ret float %0
}

; VFP2: test:
; VFP2: 	vdiv.f32	s{{.}}, s{{.}}, s{{.}}

; NFP1: test:
; NFP1: 	vdiv.f32	s{{.}}, s{{.}}, s{{.}}
; NFP0: test:
; NFP0: 	vdiv.f32	s{{.}}, s{{.}}, s{{.}}

; CORTEXA8: test:
; CORTEXA8: 	vdiv.f32	s{{.}}, s{{.}}, s{{.}}
; CORTEXA9: test:
; CORTEXA9: 	vdiv.f32	s{{.}}, s{{.}}, s{{.}}
Convert ARM tests to FileCheck for PR5307. llvm-svn: 89593 2009-11-22 15:23:33 +01:00			`; RUN: llc < %s -march=arm -mattr=+vfp2 \| FileCheck %s -check-prefix=VFP2`
switch the flag for using NEON for SP floating point to a subtarget 'feature'. Re-commit. This time complete with testsuite updates. llvm-svn: 99570 2010-03-26 00:47:34 +01:00			`; RUN: llc < %s -march=arm -mattr=+neon \| FileCheck %s -check-prefix=NFP0`
Convert ARM tests to FileCheck for PR5307. llvm-svn: 89593 2009-11-22 15:23:33 +01:00			`; RUN: llc < %s -march=arm -mcpu=cortex-a8 \| FileCheck %s -check-prefix=CORTEXA8`
			`; RUN: llc < %s -march=arm -mcpu=cortex-a9 \| FileCheck %s -check-prefix=CORTEXA9`
Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations. llvm-svn: 78081 2009-08-04 19:53:06 +02:00
			`define float @test(float %a, float %b) {`
			`entry:`
			`%0 = fdiv float %a, %b`
			`ret float %0`
			`}`

Convert ARM tests to FileCheck for PR5307. llvm-svn: 89593 2009-11-22 15:23:33 +01:00			`; VFP2: test:`
Remove some register allocation order dependencies. llvm-svn: 172874 2013-01-19 01:03:32 +01:00			`; VFP2: vdiv.f32 s{{.}}, s{{.}}, s{{.}}`
Convert ARM tests to FileCheck for PR5307. llvm-svn: 89593 2009-11-22 15:23:33 +01:00
			`; NFP1: test:`
Remove some register allocation order dependencies. llvm-svn: 172874 2013-01-19 01:03:32 +01:00			`; NFP1: vdiv.f32 s{{.}}, s{{.}}, s{{.}}`
Convert ARM tests to FileCheck for PR5307. llvm-svn: 89593 2009-11-22 15:23:33 +01:00			`; NFP0: test:`
Remove some register allocation order dependencies. llvm-svn: 172874 2013-01-19 01:03:32 +01:00			`; NFP0: vdiv.f32 s{{.}}, s{{.}}, s{{.}}`
Convert ARM tests to FileCheck for PR5307. llvm-svn: 89593 2009-11-22 15:23:33 +01:00
			`; CORTEXA8: test:`
Remove some register allocation order dependencies. llvm-svn: 172874 2013-01-19 01:03:32 +01:00			`; CORTEXA8: vdiv.f32 s{{.}}, s{{.}}, s{{.}}`
Convert ARM tests to FileCheck for PR5307. llvm-svn: 89593 2009-11-22 15:23:33 +01:00			`; CORTEXA9: test:`
Avoid write-after-write issue hazards for Cortex-A9. Add a avoidWriteAfterWrite() target hook to identify register classes that suffer from write-after-write hazards. For those register classes, try to avoid writing the same register in two consecutive instructions. This is currently disabled by default. We should not spill to avoid hazards! The command line flag -avoid-waw-hazard can be used to enable waw avoidance. llvm-svn: 129772 2011-04-19 20:11:45 +02:00			`; CORTEXA9: vdiv.f32 s{{.}}, s{{.}}, s{{.}}`