llvm-mirror/test/CodeGen/Hexagon/args.ll

; RUN: true
; DISABLED: llc -march=hexagon -mcpu=hexagonv4 -disable-dfa-sched < %s | FileCheck %s
; CHECK: r[[T0:[0-9]+]] = #7
; CHECK: memw(r29 + #0) = r[[T0]]
; CHECK: r0 = #1
; CHECK: r1 = #2
; CHECK: r2 = #3
; CHECK: r3 = #4
; CHECK: r4 = #5
; CHECK: r5 = #6


define void @foo() nounwind {
entry:
  call void @bar(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7)
  ret void
}

declare void @bar(i32, i32, i32, i32, i32, i32, i32)
Disable Hexagon test temporarily. There is an assert at line 558 in ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA). This assert needs to addressed for post RA scheduler. Until that assert is addressed, any passes that uses post ra scheduler will fail. So, I am temporarily disabling the hexagon tests until that fix is in. The assert is as follows: assert(!MI->isTerminator() && !MI->isLabel() && "Cannot schedule terminators or labels!"); llvm-svn: 154617 2012-04-12 23:06:54 +02:00			`; RUN: true`
			`; DISABLED: llc -march=hexagon -mcpu=hexagonv4 -disable-dfa-sched < %s \| FileCheck %s`
Hexagon backend support llvm-svn: 146412 2011-12-12 22:14:40 +01:00			`; CHECK: r[[T0:[0-9]+]] = #7`
			`; CHECK: memw(r29 + #0) = r[[T0]]`
			`; CHECK: r0 = #1`
			`; CHECK: r1 = #2`
			`; CHECK: r2 = #3`
			`; CHECK: r3 = #4`
			`; CHECK: r4 = #5`
			`; CHECK: r5 = #6`


			`define void @foo() nounwind {`
			`entry:`
			`call void @bar(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7)`
			`ret void`
			`}`

			`declare void @bar(i32, i32, i32, i32, i32, i32, i32)`