llvm-mirror/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt

# RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s
# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s

# None of these instructions should be classified as unpredictable:

# CHECK-NOT: potentially undefined instruction encoding

# Stores from duplicated registers should be fine.
0xe3 0x0f 0x80 0xa8
# CHECK: stp x3, x3, [sp], #0

# d5 != x5 so "ldp d5, d6, [x5], #24" is fine.
0xa5 0x98 0xc1 0x6c
# CHECK: ldp d5, d6, [x5], #24

# xzr != sp so "stp xzr, xzr, [sp], #8" is fine.
0xff 0xff 0x80 0xa8
# CHECK: stp xzr, xzr, [sp], #8
[AArch64] Make the use of FP instructions optional, but enabled by default. This adds a new subtarget feature called FPARMv8 (implied by NEON), and predicates the support of the FP instructions and registers on this feature. llvm-svn: 193739 2013-10-31 09:32:11 +00:00			`# RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s 2>&1 \| FileCheck %s`
AArch64/ARM64: port basic disassembly tests to ARM64. llvm-svn: 207753 2014-05-01 12:29:56 +00:00			`# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s 2>&1 \| FileCheck %s`
Add AArch64 as an experimental target. This patch adds support for AArch64 (ARM's 64-bit architecture) to LLVM in the "experimental" category. Currently, it won't be built unless requested explicitly. This initial commit should have support for: + Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions (except the late addition CRC instructions). + CodeGen features required for C++03 and C99. + Compilation for the "small" memory model: code+static data < 4GB. + Absolute and position-independent code. + GNU-style (i.e. "__thread") TLS. + Debugging information. The principal omission, currently, is performance tuning. This patch excludes the NEON support also reviewed due to an outbreak of batshit insanity in our legal department. That will be committed soon bringing the changes to precisely what has been approved. Further reviews would be gratefully received. llvm-svn: 174054 2013-01-31 12:12:40 +00:00
			`# None of these instructions should be classified as unpredictable:`

			`# CHECK-NOT: potentially undefined instruction encoding`

			`# Stores from duplicated registers should be fine.`
			`0xe3 0x0f 0x80 0xa8`
			`# CHECK: stp x3, x3, [sp], #0`

			`# d5 != x5 so "ldp d5, d6, [x5], #24" is fine.`
			`0xa5 0x98 0xc1 0x6c`
			`# CHECK: ldp d5, d6, [x5], #24`

			`# xzr != sp so "stp xzr, xzr, [sp], #8" is fine.`
			`0xff 0xff 0x80 0xa8`
			`# CHECK: stp xzr, xzr, [sp], #8`