2021-05-29 16:11:37 +02:00
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# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
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[RISCV] Add instruction definition for dret
Summary:
The instruction dret is used to return from debug mode and is defined in the
RISC-V debug mode spec.
https://github.com/riscv/riscv-opcodes/blob/master/opcodes-system
Reviewers: apazos, asb, lenary, luismarques
Reviewed By: apazos
Subscribers: jfb, hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, sameer.abuasal, evandro, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78583
2020-04-24 22:15:51 +02:00
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# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
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2021-05-29 16:11:37 +02:00
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# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
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[RISCV] Add instruction definition for dret
Summary:
The instruction dret is used to return from debug mode and is defined in the
RISC-V debug mode spec.
https://github.com/riscv/riscv-opcodes/blob/master/opcodes-system
Reviewers: apazos, asb, lenary, luismarques
Reviewed By: apazos
Subscribers: jfb, hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, sameer.abuasal, evandro, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78583
2020-04-24 22:15:51 +02:00
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# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
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# RUN: | llvm-objdump -M no-aliases -d - \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
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# RUN: | llvm-objdump -M no-aliases -d - \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
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# CHECK-INST: dret
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# CHECK: encoding: [0x73,0x00,0x20,0x7b]
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dret
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