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llvm-mirror/test/MC/ARM/neon-cmp-encoding.s

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Fix misspelled target triples in MC/ARM test commands. llvm-svn: 121901
2010-12-15 23:14:01 +01:00
@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
Convert this test to .s form. llvm-svn: 117683
2010-10-29 20:58:30 +02:00
vceq.i8 d16, d16, d17
vceq.i16 d16, d16, d17
vceq.i32 d16, d16, d17
vceq.f32 d16, d16, d17
vceq.i8 q8, q8, q9
vceq.i16 q8, q8, q9
vceq.i32 q8, q8, q9
vceq.f32 q8, q8, q9
Clean up formatting a bit. llvm-svn: 137393
2011-08-12 01:57:17 +02:00
@ CHECK: vceq.i8 d16, d16, d17 @ encoding: [0xb1,0x08,0x40,0xf3]
@ CHECK: vceq.i16 d16, d16, d17 @ encoding: [0xb1,0x08,0x50,0xf3]
@ CHECK: vceq.i32 d16, d16, d17 @ encoding: [0xb1,0x08,0x60,0xf3]
@ CHECK: vceq.f32 d16, d16, d17 @ encoding: [0xa1,0x0e,0x40,0xf2]
@ CHECK: vceq.i8 q8, q8, q9 @ encoding: [0xf2,0x08,0x40,0xf3]
@ CHECK: vceq.i16 q8, q8, q9 @ encoding: [0xf2,0x08,0x50,0xf3]
@ CHECK: vceq.i32 q8, q8, q9 @ encoding: [0xf2,0x08,0x60,0xf3]
@ CHECK: vceq.f32 q8, q8, q9 @ encoding: [0xe2,0x0e,0x40,0xf2]
Convert this test to .s form. llvm-svn: 117683
2010-10-29 20:58:30 +02:00
vcge.s8 d16, d16, d17
vcge.s16 d16, d16, d17
vcge.s32 d16, d16, d17
vcge.u8 d16, d16, d17
vcge.u16 d16, d16, d17
vcge.u32 d16, d16, d17
vcge.f32 d16, d16, d17
vcge.s8 q8, q8, q9
vcge.s16 q8, q8, q9
vcge.s32 q8, q8, q9
vcge.u8 q8, q8, q9
vcge.u16 q8, q8, q9
vcge.u32 q8, q8, q9
vcge.f32 q8, q8, q9
vacge.f32 d16, d16, d17
vacge.f32 q8, q8, q9
Clean up formatting a bit. llvm-svn: 137393
2011-08-12 01:57:17 +02:00
@ CHECK: vcge.s8 d16, d16, d17 @ encoding: [0xb1,0x03,0x40,0xf2]
@ CHECK: vcge.s16 d16, d16, d17 @ encoding: [0xb1,0x03,0x50,0xf2]
@ CHECK: vcge.s32 d16, d16, d17 @ encoding: [0xb1,0x03,0x60,0xf2]
@ CHECK: vcge.u8 d16, d16, d17 @ encoding: [0xb1,0x03,0x40,0xf3]
@ CHECK: vcge.u16 d16, d16, d17 @ encoding: [0xb1,0x03,0x50,0xf3]
@ CHECK: vcge.u32 d16, d16, d17 @ encoding: [0xb1,0x03,0x60,0xf3]
@ CHECK: vcge.f32 d16, d16, d17 @ encoding: [0xa1,0x0e,0x40,0xf3]
@ CHECK: vcge.s8 q8, q8, q9 @ encoding: [0xf2,0x03,0x40,0xf2]
@ CHECK: vcge.s16 q8, q8, q9 @ encoding: [0xf2,0x03,0x50,0xf2]
@ CHECK: vcge.s32 q8, q8, q9 @ encoding: [0xf2,0x03,0x60,0xf2]
@ CHECK: vcge.u8 q8, q8, q9 @ encoding: [0xf2,0x03,0x40,0xf3]
@ CHECK: vcge.u16 q8, q8, q9 @ encoding: [0xf2,0x03,0x50,0xf3]
@ CHECK: vcge.u32 q8, q8, q9 @ encoding: [0xf2,0x03,0x60,0xf3]
@ CHECK: vcge.f32 q8, q8, q9 @ encoding: [0xe2,0x0e,0x40,0xf3]
@ CHECK: vacge.f32 d16, d16, d17 @ encoding: [0xb1,0x0e,0x40,0xf3]
@ CHECK: vacge.f32 q8, q8, q9 @ encoding: [0xf2,0x0e,0x40,0xf3]
Convert this test to .s form. llvm-svn: 117683
2010-10-29 20:58:30 +02:00
vcgt.s8 d16, d16, d17
vcgt.s16 d16, d16, d17
vcgt.s32 d16, d16, d17
vcgt.u8 d16, d16, d17
vcgt.u16 d16, d16, d17
vcgt.u32 d16, d16, d17
vcgt.f32 d16, d16, d17
vcgt.s8 q8, q8, q9
vcgt.s16 q8, q8, q9
vcgt.s32 q8, q8, q9
vcgt.u8 q8, q8, q9
vcgt.u16 q8, q8, q9
vcgt.u32 q8, q8, q9
vcgt.f32 q8, q8, q9
vacgt.f32 d16, d16, d17
vacgt.f32 q8, q8, q9
Clean up formatting a bit. llvm-svn: 137393
2011-08-12 01:57:17 +02:00
@ CHECK: vcgt.s8 d16, d16, d17 @ encoding: [0xa1,0x03,0x40,0xf2]
@ CHECK: vcgt.s16 d16, d16, d17 @ encoding: [0xa1,0x03,0x50,0xf2]
@ CHECK: vcgt.s32 d16, d16, d17 @ encoding: [0xa1,0x03,0x60,0xf2]
@ CHECK: vcgt.u8 d16, d16, d17 @ encoding: [0xa1,0x03,0x40,0xf3]
@ CHECK: vcgt.u16 d16, d16, d17 @ encoding: [0xa1,0x03,0x50,0xf3]
@ CHECK: vcgt.u32 d16, d16, d17 @ encoding: [0xa1,0x03,0x60,0xf3]
@ CHECK: vcgt.f32 d16, d16, d17 @ encoding: [0xa1,0x0e,0x60,0xf3]
@ CHECK: vcgt.s8 q8, q8, q9 @ encoding: [0xe2,0x03,0x40,0xf2]
@ CHECK: vcgt.s16 q8, q8, q9 @ encoding: [0xe2,0x03,0x50,0xf2]
@ CHECK: vcgt.s32 q8, q8, q9 @ encoding: [0xe2,0x03,0x60,0xf2]
@ CHECK: vcgt.u8 q8, q8, q9 @ encoding: [0xe2,0x03,0x40,0xf3]
@ CHECK: vcgt.u16 q8, q8, q9 @ encoding: [0xe2,0x03,0x50,0xf3]
@ CHECK: vcgt.u32 q8, q8, q9 @ encoding: [0xe2,0x03,0x60,0xf3]
@ CHECK: vcgt.f32 q8, q8, q9 @ encoding: [0xe2,0x0e,0x60,0xf3]
@ CHECK: vacgt.f32 d16, d16, d17 @ encoding: [0xb1,0x0e,0x60,0xf3]
@ CHECK: vacgt.f32 q8, q8, q9 @ encoding: [0xf2,0x0e,0x60,0xf3]
Convert this test to .s form. llvm-svn: 117683
2010-10-29 20:58:30 +02:00
vtst.8 d16, d16, d17
vtst.16 d16, d16, d17
vtst.32 d16, d16, d17
vtst.8 q8, q8, q9
vtst.16 q8, q8, q9
vtst.32 q8, q8, q9
Add support for ARM's specialized vector-compare-against-zero instructions. llvm-svn: 118453
2010-11-09 00:21:22 +01:00
Clean up formatting a bit. llvm-svn: 137393
2011-08-12 01:57:17 +02:00
@ CHECK: vtst.8 d16, d16, d17 @ encoding: [0xb1,0x08,0x40,0xf2]
@ CHECK: vtst.16 d16, d16, d17 @ encoding: [0xb1,0x08,0x50,0xf2]
@ CHECK: vtst.32 d16, d16, d17 @ encoding: [0xb1,0x08,0x60,0xf2]
@ CHECK: vtst.8 q8, q8, q9 @ encoding: [0xf2,0x08,0x40,0xf2]
@ CHECK: vtst.16 q8, q8, q9 @ encoding: [0xf2,0x08,0x50,0xf2]
@ CHECK: vtst.32 q8, q8, q9 @ encoding: [0xf2,0x08,0x60,0xf2]
vceq.i8 d16, d16, #0
vcge.s8 d16, d16, #0
vcle.s8 d16, d16, #0
vcgt.s8 d16, d16, #0
vclt.s8 d16, d16, #0
@ CHECK: vceq.i8 d16, d16, #0 @ encoding: [0x20,0x01,0xf1,0xf3]
@ CHECK: vcge.s8 d16, d16, #0 @ encoding: [0xa0,0x00,0xf1,0xf3]
@ CHECK: vcle.s8 d16, d16, #0 @ encoding: [0xa0,0x01,0xf1,0xf3]
@ CHECK: vcgt.s8 d16, d16, #0 @ encoding: [0x20,0x00,0xf1,0xf3]
@ CHECK: vclt.s8 d16, d16, #0 @ encoding: [0x20,0x02,0xf1,0xf3]
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