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llvm-mirror/test/MC/ARM/arm_instructions.s

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Mark ARM subtarget features that are available for the assembler. llvm-svn: 117929
2010-11-01 17:59:54 +01:00
@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s
MC/ARM: Add basic support for handling predication by parsing it out of the mnemonic into a separate operand form. llvm-svn: 110794
2010-08-11 08:37:20 +02:00
Add encoding for ARM "trap" instruction. llvm-svn: 119938
2010-11-21 12:05:29 +01:00
@ CHECK: trap
@ CHECK: encoding: [0xfe,0xde,0xff,0xe7]
trap
fix the asmmatcher generator to handle targets with no RegisterPrefix (like ARM) correctly. With this change, we can now match "bx lr" because we recognize lr as a register. llvm-svn: 117606
2010-10-28 23:28:42 +02:00
@ CHECK: bx lr
@ CHECK: encoding: [0x1e,0xff,0x2f,0xe1]
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work with immediates up to 16-bits in size. The same logic is applied to other LDR encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in VLDR's case). Removing the "12" allows it to be more generic. llvm-svn: 118094
2010-11-02 23:31:46 +01:00
bx lr
most simple arm instructions match correctly now, it looks like we're not handling [] operands though llvm-svn: 117607
2010-10-28 23:31:07 +02:00
@ CHECK: vqdmull.s32 q8, d17, d16
@ CHECK: encoding: [0xa0,0x0d,0xe1,0xf2]
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work with immediates up to 16-bits in size. The same logic is applied to other LDR encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in VLDR's case). Removing the "12" allows it to be more generic. llvm-svn: 118094
2010-11-02 23:31:46 +01:00
vqdmull.s32 q8, d17, d16
Test encodings for LDM and STM. llvm-svn: 119315
2010-11-16 02:38:20 +01:00
Add some more MC tests for ARM arithmetic instructions that update or don't update the condition codes. These come from my test generator and are just the ones that MC currently assembles correctly. llvm-svn: 121830
2010-12-15 02:24:36 +01:00
@ CHECK: and r1, r2, r3 @ encoding: [0x03,0x10,0x02,0xe0]
and r1,r2,r3
Enable some tests we now handle correctly. llvm-svn: 135185
2011-07-14 23:02:23 +02:00
@ CHECK: ands r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0]
Add some more MC tests for ARM arithmetic instructions that update or don't update the condition codes. These come from my test generator and are just the ones that MC currently assembles correctly. llvm-svn: 121830
2010-12-15 02:24:36 +01:00
ands r1,r2,r3
@ CHECK: eor r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0]
eor r1,r2,r3
Enable some tests we now handle correctly. llvm-svn: 135185
2011-07-14 23:02:23 +02:00
@ CHECK: eors r1, r2, r3 @ encoding: [0x03,0x10,0x32,0xe0]
Add some more MC tests for ARM arithmetic instructions that update or don't update the condition codes. These come from my test generator and are just the ones that MC currently assembles correctly. llvm-svn: 121830
2010-12-15 02:24:36 +01:00
eors r1,r2,r3
@ CHECK: sub r1, r2, r3 @ encoding: [0x03,0x10,0x42,0xe0]
sub r1,r2,r3
Enable some tests we now handle correctly. llvm-svn: 135185
2011-07-14 23:02:23 +02:00
@ CHECK: subs r1, r2, r3 @ encoding: [0x03,0x10,0x52,0xe0]
Add some more MC tests for ARM arithmetic instructions that update or don't update the condition codes. These come from my test generator and are just the ones that MC currently assembles correctly. llvm-svn: 121830
2010-12-15 02:24:36 +01:00
subs r1,r2,r3
@ CHECK: add r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe0]
add r1,r2,r3
Enable some tests we now handle correctly. llvm-svn: 135185
2011-07-14 23:02:23 +02:00
@ CHECK: adds r1, r2, r3 @ encoding: [0x03,0x10,0x92,0xe0]
Add some more MC tests for ARM arithmetic instructions that update or don't update the condition codes. These come from my test generator and are just the ones that MC currently assembles correctly. llvm-svn: 121830
2010-12-15 02:24:36 +01:00
adds r1,r2,r3
@ CHECK: adc r1, r2, r3 @ encoding: [0x03,0x10,0xa2,0xe0]
adc r1,r2,r3
@ CHECK: bic r1, r2, r3 @ encoding: [0x03,0x10,0xc2,0xe1]
bic r1,r2,r3
Enable some tests we now handle correctly. llvm-svn: 135185
2011-07-14 23:02:23 +02:00
@ CHECK: bics r1, r2, r3 @ encoding: [0x03,0x10,0xd2,0xe1]
Add some more MC tests for ARM arithmetic instructions that update or don't update the condition codes. These come from my test generator and are just the ones that MC currently assembles correctly. llvm-svn: 121830
2010-12-15 02:24:36 +01:00
bics r1,r2,r3
@ CHECK: mov r1, r2 @ encoding: [0x02,0x10,0xa0,0xe1]
mov r1,r2
@ CHECK: mvn r1, r2 @ encoding: [0x02,0x10,0xe0,0xe1]
mvn r1,r2
Enable some tests we now handle correctly. llvm-svn: 135185
2011-07-14 23:02:23 +02:00
@ CHECK: mvns r1, r2 @ encoding: [0x02,0x10,0xf0,0xe1]
Add some more MC tests for ARM arithmetic instructions that update or don't update the condition codes. These come from my test generator and are just the ones that MC currently assembles correctly. llvm-svn: 121830
2010-12-15 02:24:36 +01:00
mvns r1,r2
Add support for parsing and encoding ARM's official syntax for the BFI instruction llvm-svn: 123770
2011-01-18 21:45:56 +01:00
@ CHECK: bfi r0, r0, #5, #7 @ encoding: [0x90,0x02,0xcb,0xe7]
bfi r0, r0, #5, #7
Follow the current hack set and enable the correct parsing of bkpt while in thumb mode. llvm-svn: 123772
2011-01-18 21:55:11 +01:00
@ CHECK: bkpt #10 @ encoding: [0x7a,0x00,0x20,0xe1]
bkpt #10
Fix the encoding of t2ISB by using the right class and also parse it correctly llvm-svn: 123776
2011-01-18 22:17:09 +01:00
- Use a more appropriate name for Owen's ARM Parser isMCR hack since the same operands can be present in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions. - Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t hem. llvm-svn: 123927
2011-01-20 19:06:58 +01:00
@ CHECK: cdp p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xee]
cdp p7, #1, c1, c1, c1, #4
@ CHECK: cdp2 p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xfe]
cdp2 p7, #1, c1, c1, c1, #4
Add support to the ARM asm parser for the register-shifted-register forms of basic instructions like ADD. More work left to be done to support other instances of shifter ops in the ISA. llvm-svn: 127917
2011-03-18 23:50:18 +01:00
@ CHECK: add r1, r2, r3, lsl r4 @ encoding: [0x13,0x14,0x82,0xe0]
add r1, r2, r3, lsl r4
Add asm parsing support w/ testcases for strex/ldrex family of instructions llvm-svn: 128236
2011-03-24 22:04:58 +01:00
Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value must be encoded decremented by one. Only add encoding tests for ssat16 because ssat can't be parsed yet. llvm-svn: 132324
2011-05-31 05:33:27 +02:00
@ CHECK: ssat16 r0, #7, r0 @ encoding: [0x30,0x0f,0xa6,0xe6]
ssat16 r0, #7, r0
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