2021-01-06 18:35:52 +01:00
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; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1010 -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck --check-prefix=GCN %s
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2019-06-20 18:29:40 +02:00
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; GCN-LABEL: _amdgpu_hs_main:
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define amdgpu_hs void @_amdgpu_hs_main() #0 {
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.entry:
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ret void
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}
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; GCN-LABEL: _amdgpu_ps_main:
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; GCN: s_and_saveexec_b64
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define amdgpu_ps void @_amdgpu_ps_main(i32 %arg) local_unnamed_addr #1 {
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.entry:
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%tmp = tail call float @llvm.amdgcn.interp.p2(float undef, float undef, i32 1, i32 0, i32 %arg) #2
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%tmp1 = tail call float @llvm.amdgcn.image.sample.2d.f32.f32(i32 1, float undef, float %tmp, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
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%tmp2 = fcmp olt float %tmp1, 5.000000e-01
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br i1 %tmp2, label %bb, label %l
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bb: ; preds = %.entry
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unreachable
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l: ; preds = %.entry
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ret void
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}
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; GCN-LABEL: _amdgpu_gs_main:
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define amdgpu_gs void @_amdgpu_gs_main() #4 {
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.entry:
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ret void
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}
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declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #2
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declare float @llvm.amdgcn.image.sample.2d.f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #3
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attributes #0 = { "amdgpu-max-work-group-size"="128" "target-features"=",+wavefrontsize32" }
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attributes #1 = { "target-features"=",+wavefrontsize64" }
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attributes #2 = { nounwind readnone speculatable }
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attributes #3 = { nounwind readonly }
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attributes #4 = { "target-features"=",+wavefrontsize32" }
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