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llvm-mirror/test/CodeGen/Mips/octeon.ll

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[mips] Use --check-prefixes where appropriate. NFC. llvm-svn: 273669
2016-06-24 14:23:17 +02:00
; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon | FileCheck %s -check-prefixes=ALL,OCTEON
; RUN: llc -O1 < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,MIPS64
[Mips] Fix for BBIT octeon instruction This patch enables control flow optimization for variations of BBIT instruction. In this case optimization removes unnecessary branch after BBIT instruction. Differential Revision: https://reviews.llvm.org/D35359 llvm-svn: 309679
2017-08-01 15:42:45 +02:00
; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon -relocation-model=pic | FileCheck %s -check-prefixes=ALL,OCTEON-PIC
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 12:51:58 +01:00
[mips] Add more Octeon cnMips instructions Adds the instructions ext/ext32/cins/cins32. It also changes pop/dpop to accept the two operand version and adds a simple pattern to generate baddu. Tests for the two operand versions (including baddu/dmul/dpop/pop) and the code generation pattern for baddu are included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205449
2014-04-02 20:40:43 +02:00
define i64 @addi64(i64 %a, i64 %b) nounwind {
entry:
[mips] Add registers and ALL check prefix to octeon test case. No functional change. Reviewed by D. Sanders llvm-svn: 226574
2015-01-20 17:14:02 +01:00
; ALL-LABEL: addi64:
[mips] Add more Octeon cnMips instructions Adds the instructions ext/ext32/cins/cins32. It also changes pop/dpop to accept the two operand version and adds a simple pattern to generate baddu. Tests for the two operand versions (including baddu/dmul/dpop/pop) and the code generation pattern for baddu are included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205449
2014-04-02 20:40:43 +02:00
; OCTEON: jr $ra
; OCTEON: baddu $2, $4, $5
[mips] Add registers and ALL check prefix to octeon test case. No functional change. Reviewed by D. Sanders llvm-svn: 226574
2015-01-20 17:14:02 +01:00
; MIPS64: daddu $[[T0:[0-9]+]], $4, $5
; MIPS64: jr $ra
; MIPS64: andi $2, $[[T0]], 255
[mips] Add more Octeon cnMips instructions Adds the instructions ext/ext32/cins/cins32. It also changes pop/dpop to accept the two operand version and adds a simple pattern to generate baddu. Tests for the two operand versions (including baddu/dmul/dpop/pop) and the code generation pattern for baddu are included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205449
2014-04-02 20:40:43 +02:00
%add = add i64 %a, %b
%and = and i64 %add, 255
ret i64 %and
}
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 12:51:58 +01:00
define i64 @mul(i64 %a, i64 %b) nounwind {
entry:
[mips] Add registers and ALL check prefix to octeon test case. No functional change. Reviewed by D. Sanders llvm-svn: 226574
2015-01-20 17:14:02 +01:00
; ALL-LABEL: mul:
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 12:51:58 +01:00
; OCTEON: jr $ra
; OCTEON: dmul $2, $4, $5
[mips] Add registers and ALL check prefix to octeon test case. No functional change. Reviewed by D. Sanders llvm-svn: 226574
2015-01-20 17:14:02 +01:00
; MIPS64: dmult $4, $5
; MIPS64: jr $ra
; MIPS64: mflo $2
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 12:51:58 +01:00
%res = mul i64 %a, %b
ret i64 %res
}
[mips] Refine octeon instructions seq/seqi/sne/snei This commit refines the pattern for the octeon seq/seqi/sne/snei instructions. The target register is set to 0 or 1 according to the result of the comparison. In C, this is something like rd = (unsigned long)(rs == rt) This commit adds a zext to bring the result to i64. With this change the instruction is selected for this type of code. (gcc produces the same code for the above C code.) llvm-svn: 225968
2015-01-14 11:19:09 +01:00
define i64 @cmpeq(i64 %a, i64 %b) nounwind {
entry:
[mips] Add registers and ALL check prefix to octeon test case. No functional change. Reviewed by D. Sanders llvm-svn: 226574
2015-01-20 17:14:02 +01:00
; ALL-LABEL: cmpeq:
[mips] Refine octeon instructions seq/seqi/sne/snei This commit refines the pattern for the octeon seq/seqi/sne/snei instructions. The target register is set to 0 or 1 according to the result of the comparison. In C, this is something like rd = (unsigned long)(rs == rt) This commit adds a zext to bring the result to i64. With this change the instruction is selected for this type of code. (gcc produces the same code for the above C code.) llvm-svn: 225968
2015-01-14 11:19:09 +01:00
; OCTEON: jr $ra
; OCTEON: seq $2, $4, $5
[mips] Add registers and ALL check prefix to octeon test case. No functional change. Reviewed by D. Sanders llvm-svn: 226574
2015-01-20 17:14:02 +01:00
; MIPS64: xor $[[T0:[0-9]+]], $4, $5
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-01 21:25:43 +01:00
; MIPS64: sltiu $[[T1:[0-9]+]], $[[T0]], 1
; MIPS64: dsll $[[T2:[0-9]+]], $[[T1]], 32
[mips] Refine octeon instructions seq/seqi/sne/snei This commit refines the pattern for the octeon seq/seqi/sne/snei instructions. The target register is set to 0 or 1 according to the result of the comparison. In C, this is something like rd = (unsigned long)(rs == rt) This commit adds a zext to bring the result to i64. With this change the instruction is selected for this type of code. (gcc produces the same code for the above C code.) llvm-svn: 225968
2015-01-14 11:19:09 +01:00
; MIPS64: jr $ra
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-01 21:25:43 +01:00
; MIPS64: dsrl $2, $[[T2]], 32
[mips] Refine octeon instructions seq/seqi/sne/snei This commit refines the pattern for the octeon seq/seqi/sne/snei instructions. The target register is set to 0 or 1 according to the result of the comparison. In C, this is something like rd = (unsigned long)(rs == rt) This commit adds a zext to bring the result to i64. With this change the instruction is selected for this type of code. (gcc produces the same code for the above C code.) llvm-svn: 225968
2015-01-14 11:19:09 +01:00
%res = icmp eq i64 %a, %b
%res2 = zext i1 %res to i64
ret i64 %res2
}
define i64 @cmpeqi(i64 %a) nounwind {
entry:
[mips] Add registers and ALL check prefix to octeon test case. No functional change. Reviewed by D. Sanders llvm-svn: 226574
2015-01-20 17:14:02 +01:00
; ALL-LABEL: cmpeqi:
[mips] Refine octeon instructions seq/seqi/sne/snei This commit refines the pattern for the octeon seq/seqi/sne/snei instructions. The target register is set to 0 or 1 according to the result of the comparison. In C, this is something like rd = (unsigned long)(rs == rt) This commit adds a zext to bring the result to i64. With this change the instruction is selected for this type of code. (gcc produces the same code for the above C code.) llvm-svn: 225968
2015-01-14 11:19:09 +01:00
; OCTEON: jr $ra
; OCTEON: seqi $2, $4, 42
[mips] Add registers and ALL check prefix to octeon test case. No functional change. Reviewed by D. Sanders llvm-svn: 226574
2015-01-20 17:14:02 +01:00
; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 42
; MIPS64: xor $[[T1:[0-9]+]], $4, $[[T0]]
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-01 21:25:43 +01:00
; MIPS64: sltiu $[[T2:[0-9]+]], $[[T1]], 1
; MIPS64: dsll $[[T3:[0-9]+]], $[[T2]], 32
[mips] Refine octeon instructions seq/seqi/sne/snei This commit refines the pattern for the octeon seq/seqi/sne/snei instructions. The target register is set to 0 or 1 according to the result of the comparison. In C, this is something like rd = (unsigned long)(rs == rt) This commit adds a zext to bring the result to i64. With this change the instruction is selected for this type of code. (gcc produces the same code for the above C code.) llvm-svn: 225968
2015-01-14 11:19:09 +01:00
; MIPS64: jr $ra
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-01 21:25:43 +01:00
; MIPS64: dsrl $2, $[[T3]], 32
[mips] Refine octeon instructions seq/seqi/sne/snei This commit refines the pattern for the octeon seq/seqi/sne/snei instructions. The target register is set to 0 or 1 according to the result of the comparison. In C, this is something like rd = (unsigned long)(rs == rt) This commit adds a zext to bring the result to i64. With this change the instruction is selected for this type of code. (gcc produces the same code for the above C code.) llvm-svn: 225968
2015-01-14 11:19:09 +01:00
%res = icmp eq i64 %a, 42
%res2 = zext i1 %res to i64
ret i64 %res2
}
define i64 @cmpne(i64 %a, i64 %b) nounwind {
entry:
[mips] Add registers and ALL check prefix to octeon test case. No functional change. Reviewed by D. Sanders llvm-svn: 226574
2015-01-20 17:14:02 +01:00
; ALL-LABEL: cmpne:
[mips] Refine octeon instructions seq/seqi/sne/snei This commit refines the pattern for the octeon seq/seqi/sne/snei instructions. The target register is set to 0 or 1 according to the result of the comparison. In C, this is something like rd = (unsigned long)(rs == rt) This commit adds a zext to bring the result to i64. With this change the instruction is selected for this type of code. (gcc produces the same code for the above C code.) llvm-svn: 225968
2015-01-14 11:19:09 +01:00
; OCTEON: jr $ra
; OCTEON: sne $2, $4, $5
[mips] Add registers and ALL check prefix to octeon test case. No functional change. Reviewed by D. Sanders llvm-svn: 226574
2015-01-20 17:14:02 +01:00
; MIPS64: xor $[[T0:[0-9]+]], $4, $5
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-01 21:25:43 +01:00
; MIPS64: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
; MIPS64: dsll $[[T2:[0-9]+]], $[[T1]], 32
[mips] Refine octeon instructions seq/seqi/sne/snei This commit refines the pattern for the octeon seq/seqi/sne/snei instructions. The target register is set to 0 or 1 according to the result of the comparison. In C, this is something like rd = (unsigned long)(rs == rt) This commit adds a zext to bring the result to i64. With this change the instruction is selected for this type of code. (gcc produces the same code for the above C code.) llvm-svn: 225968
2015-01-14 11:19:09 +01:00
; MIPS64: jr $ra
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-01 21:25:43 +01:00
; MIPS64: dsrl $2, $[[T2]], 32
[mips] Refine octeon instructions seq/seqi/sne/snei This commit refines the pattern for the octeon seq/seqi/sne/snei instructions. The target register is set to 0 or 1 according to the result of the comparison. In C, this is something like rd = (unsigned long)(rs == rt) This commit adds a zext to bring the result to i64. With this change the instruction is selected for this type of code. (gcc produces the same code for the above C code.) llvm-svn: 225968
2015-01-14 11:19:09 +01:00
%res = icmp ne i64 %a, %b
%res2 = zext i1 %res to i64
ret i64 %res2
}
define i64 @cmpnei(i64 %a) nounwind {
entry:
[mips] Add registers and ALL check prefix to octeon test case. No functional change. Reviewed by D. Sanders llvm-svn: 226574
2015-01-20 17:14:02 +01:00
; ALL-LABEL: cmpnei:
[mips] Refine octeon instructions seq/seqi/sne/snei This commit refines the pattern for the octeon seq/seqi/sne/snei instructions. The target register is set to 0 or 1 according to the result of the comparison. In C, this is something like rd = (unsigned long)(rs == rt) This commit adds a zext to bring the result to i64. With this change the instruction is selected for this type of code. (gcc produces the same code for the above C code.) llvm-svn: 225968
2015-01-14 11:19:09 +01:00
; OCTEON: jr $ra
; OCTEON: snei $2, $4, 42
[mips] Add registers and ALL check prefix to octeon test case. No functional change. Reviewed by D. Sanders llvm-svn: 226574
2015-01-20 17:14:02 +01:00
; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 42
; MIPS64: xor $[[T1:[0-9]+]], $4, $[[T0]]
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-01 21:25:43 +01:00
; MIPS64: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
; MIPS64: dsll $[[T3:[0-9]+]], $[[T2]], 32
[mips] Refine octeon instructions seq/seqi/sne/snei This commit refines the pattern for the octeon seq/seqi/sne/snei instructions. The target register is set to 0 or 1 according to the result of the comparison. In C, this is something like rd = (unsigned long)(rs == rt) This commit adds a zext to bring the result to i64. With this change the instruction is selected for this type of code. (gcc produces the same code for the above C code.) llvm-svn: 225968
2015-01-14 11:19:09 +01:00
; MIPS64: jr $ra
Revert "[mips] Promote the result of SETCC nodes to GPR width." This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
2016-03-01 21:25:43 +01:00
; MIPS64: dsrl $2, $[[T3]], 32
[mips] Refine octeon instructions seq/seqi/sne/snei This commit refines the pattern for the octeon seq/seqi/sne/snei instructions. The target register is set to 0 or 1 according to the result of the comparison. In C, this is something like rd = (unsigned long)(rs == rt) This commit adds a zext to bring the result to i64. With this change the instruction is selected for this type of code. (gcc produces the same code for the above C code.) llvm-svn: 225968
2015-01-14 11:19:09 +01:00
%res = icmp ne i64 %a, 42
%res2 = zext i1 %res to i64
ret i64 %res2
}
[mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132 This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
2015-01-20 17:10:51 +01:00
[Mips] Fix for BBIT octeon instruction This patch enables control flow optimization for variations of BBIT instruction. In this case optimization removes unnecessary branch after BBIT instruction. Differential Revision: https://reviews.llvm.org/D35359 llvm-svn: 309679
2017-08-01 15:42:45 +02:00
define i64 @bbit1(i64 %a) nounwind {
[mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132 This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
2015-01-20 17:10:51 +01:00
entry:
[Mips] Fix for BBIT octeon instruction This patch enables control flow optimization for variations of BBIT instruction. In this case optimization removes unnecessary branch after BBIT instruction. Differential Revision: https://reviews.llvm.org/D35359 llvm-svn: 309679
2017-08-01 15:42:45 +02:00
; ALL-LABEL: bbit1:
; OCTEON: bbit1 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
; OCTEON-PIC-NOT: b {{[[:space:]].*}}
; OCTEON-NOT: j {{[[:space:]].*}}
[mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132 This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
2015-01-20 17:10:51 +01:00
; MIPS64: andi $[[T0:[0-9]+]], $4, 8
[mips] Correct label prefixes for N32 and N64. Summary: N32 and N64 follow the standard ELF conventions (.L) whereas O32 uses its own ($). This fixes the majority of object differences between -fintegrated-as and -fno-integrated-as. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: https://reviews.llvm.org/D22412 llvm-svn: 275967
2016-07-19 12:49:03 +02:00
; MIPS64: bnez $[[T0]], [[BB0:(\$|\.L)BB[0-9_]+]]
[mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132 This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
2015-01-20 17:10:51 +01:00
%bit = and i64 %a, 8
%res = icmp eq i64 %bit, 0
br i1 %res, label %endif, label %if
if:
ret i64 48
endif:
ret i64 12
}
[Mips] Fix for BBIT octeon instruction This patch enables control flow optimization for variations of BBIT instruction. In this case optimization removes unnecessary branch after BBIT instruction. Differential Revision: https://reviews.llvm.org/D35359 llvm-svn: 309679
2017-08-01 15:42:45 +02:00
define i64 @bbit132(i64 %a) nounwind {
[mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132 This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
2015-01-20 17:10:51 +01:00
entry:
[Mips] Fix for BBIT octeon instruction This patch enables control flow optimization for variations of BBIT instruction. In this case optimization removes unnecessary branch after BBIT instruction. Differential Revision: https://reviews.llvm.org/D35359 llvm-svn: 309679
2017-08-01 15:42:45 +02:00
; ALL-LABEL: bbit132:
; OCTEON: bbit132 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
; OCTEON-PIC-NOT: b {{[[:space:]].*}}
; OCTEON-NOT: j {{[[:space:]].*}}
[mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132 This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
2015-01-20 17:10:51 +01:00
; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 1
; MIPS64: dsll $[[T1:[0-9]+]], $[[T0]], 35
; MIPS64: and $[[T2:[0-9]+]], $4, $[[T1]]
[mips] Correct label prefixes for N32 and N64. Summary: N32 and N64 follow the standard ELF conventions (.L) whereas O32 uses its own ($). This fixes the majority of object differences between -fintegrated-as and -fno-integrated-as. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: https://reviews.llvm.org/D22412 llvm-svn: 275967
2016-07-19 12:49:03 +02:00
; MIPS64: bnez $[[T2]], [[BB0:(\$|\.L)BB[0-9_]+]]
[mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132 This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
2015-01-20 17:10:51 +01:00
%bit = and i64 %a, 34359738368
%res = icmp eq i64 %bit, 0
br i1 %res, label %endif, label %if
if:
ret i64 48
endif:
ret i64 12
}
[Mips] Fix for BBIT octeon instruction This patch enables control flow optimization for variations of BBIT instruction. In this case optimization removes unnecessary branch after BBIT instruction. Differential Revision: https://reviews.llvm.org/D35359 llvm-svn: 309679
2017-08-01 15:42:45 +02:00
define i64 @bbit0(i64 %a) nounwind {
[mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132 This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
2015-01-20 17:10:51 +01:00
entry:
[Mips] Fix for BBIT octeon instruction This patch enables control flow optimization for variations of BBIT instruction. In this case optimization removes unnecessary branch after BBIT instruction. Differential Revision: https://reviews.llvm.org/D35359 llvm-svn: 309679
2017-08-01 15:42:45 +02:00
; ALL-LABEL: bbit0:
; OCTEON: bbit0 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
; OCTEON-PIC-NOT: b {{[[:space:]].*}}
; OCTEON-NOT: j {{[[:space:]].*}}
[mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132 This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
2015-01-20 17:10:51 +01:00
; MIPS64: andi $[[T0:[0-9]+]], $4, 8
[mips] Correct label prefixes for N32 and N64. Summary: N32 and N64 follow the standard ELF conventions (.L) whereas O32 uses its own ($). This fixes the majority of object differences between -fintegrated-as and -fno-integrated-as. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: https://reviews.llvm.org/D22412 llvm-svn: 275967
2016-07-19 12:49:03 +02:00
; MIPS64: beqz $[[T0]], [[BB0:(\$|\.L)BB[0-9_]+]]
[mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132 This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
2015-01-20 17:10:51 +01:00
%bit = and i64 %a, 8
%res = icmp ne i64 %bit, 0
br i1 %res, label %endif, label %if
if:
ret i64 48
endif:
ret i64 12
}
[Mips] Fix for BBIT octeon instruction This patch enables control flow optimization for variations of BBIT instruction. In this case optimization removes unnecessary branch after BBIT instruction. Differential Revision: https://reviews.llvm.org/D35359 llvm-svn: 309679
2017-08-01 15:42:45 +02:00
define i64 @bbit032(i64 %a) nounwind {
[mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132 This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
2015-01-20 17:10:51 +01:00
entry:
[Mips] Fix for BBIT octeon instruction This patch enables control flow optimization for variations of BBIT instruction. In this case optimization removes unnecessary branch after BBIT instruction. Differential Revision: https://reviews.llvm.org/D35359 llvm-svn: 309679
2017-08-01 15:42:45 +02:00
; ALL-LABEL: bbit032:
; OCTEON: bbit032 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
; OCTEON-PIC-NOT: b {{[[:space:]].*}}
; OCTEON-NOT: j {{[[:space:]].*}}
[mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132 This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
2015-01-20 17:10:51 +01:00
; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 1
; MIPS64: dsll $[[T1:[0-9]+]], $[[T0]], 35
; MIPS64: and $[[T2:[0-9]+]], $4, $[[T1]]
[mips] Correct label prefixes for N32 and N64. Summary: N32 and N64 follow the standard ELF conventions (.L) whereas O32 uses its own ($). This fixes the majority of object differences between -fintegrated-as and -fno-integrated-as. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: https://reviews.llvm.org/D22412 llvm-svn: 275967
2016-07-19 12:49:03 +02:00
; MIPS64: beqz $[[T2]], [[BB0:(\$|\.L)BB[0-9_]+]]
[mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132 This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
2015-01-20 17:10:51 +01:00
%bit = and i64 %a, 34359738368
%res = icmp ne i64 %bit, 0
br i1 %res, label %endif, label %if
if:
ret i64 48
endif:
ret i64 12
}
[MIPS] Add support to match more patterns for BBIT instruction This patch supports one more pattern for bbit0 and bbit1 instructions, CBranchBitNum class is expanded so it can take 32 bit immidate. Differential Revision: https://reviews.llvm.org/D36222 llvm-svn: 312111
2017-08-30 13:25:38 +02:00
; extern void foo(void);
; long long var = 7;
; void bbit0i32 () {
; if ((var & 0x2)) {
; foo();
; }
; }
;
; void bbit1i32() {
; if (!(var & 0x2)) {
; foo();
; }
; }
@var = local_unnamed_addr global i64 7, align 8
define void @bbit0i32() local_unnamed_addr {
entry:
; ALL-LABEL: bbit0i32:
; OCTEON: bbit0 $1, 1, [[BB0:(\$|\.L)BB[0-9_]+]]
; OCTEON-PIC-NOT: b {{[[:space:]].*}}
; OCTEON-NOT: j {{[[:space:]].*}}
%0 = load i64, i64* @var, align 8
%and = and i64 %0, 2
%tobool = icmp eq i64 %and, 0
br i1 %tobool, label %if.end, label %if.then
if.then: ; preds = %entry
tail call void @foo() #2
br label %if.end
if.end: ; preds = %entry, %if.then
ret void
}
declare void @foo() local_unnamed_addr
define void @bbit1i32() local_unnamed_addr {
entry:
; ALL-LABEL: bbit1i32:
; OCTEON: bbit1 $1, 1, [[BB0:(\$|\.L)BB[0-9_]+]]
; OCTEON-PIC-NOT: b {{[[:space:]].*}}
; OCTEON-NOT: j {{[[:space:]].*}}
%0 = load i64, i64* @var, align 8
%and = and i64 %0, 2
%tobool = icmp eq i64 %and, 0
br i1 %tobool, label %if.then, label %if.end
if.then: ; preds = %entry
tail call void @foo() #2
br label %if.end
if.end: ; preds = %entry, %if.then
ret void
}
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