llvm-mirror/lib/Target/X86/Makefile

##===- lib/Target/X86/Makefile -----------------------------*- Makefile -*-===##
# 
#                     The LLVM Compiler Infrastructure
#
# This file was developed by the LLVM research group and is distributed under
# the University of Illinois Open Source License. See LICENSE.TXT for details.
# 
##===----------------------------------------------------------------------===##
LEVEL = ../../..
LIBRARYNAME = x86
include $(LEVEL)/Makefile.common

TARGET = X86

# Make sure that tblgen is run, first thing.
$(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
                 X86GenRegisterInfo.inc X86GenInstrNames.inc \
                 X86GenInstrInfo.inc X86GenATTAsmWriter.inc \
                 X86GenIntelAsmWriter.inc

TDFILES = $(SourceDir)/$(TARGET).td $(wildcard $(SourceDir)/*.td) \
          $(SourceDir)/../Target.td

$(TARGET)GenRegisterNames.inc::  $(TDFILES) $(TBLGEN)
	@echo "Building $(TARGET).td register names with tblgen"
	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@

$(TARGET)GenRegisterInfo.h.inc:: $(TDFILES) $(TBLGEN)
	@echo "Building $(TARGET).td register information header with tblgen"
	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@

$(TARGET)GenRegisterInfo.inc:: $(TDFILES) $(TBLGEN)
	@echo "Building $(TARGET).td register info implementation with tblgen"
	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@

$(TARGET)GenInstrNames.inc:: $(TDFILES) $(TBLGEN)
	@echo "Building $(TARGET).td instruction names with tblgen"
	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@

$(TARGET)GenInstrInfo.inc:: $(TDFILES) $(TBLGEN)
	@echo "Building $(TARGET).td instruction information with tblgen"
	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@

$(TARGET)GenATTAsmWriter.inc:: $(TDFILES) $(TBLGEN)
	@echo "Building $(TARGET).td AT&T assembly writer with tblgen"
	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-asm-writer -o $@

$(TARGET)GenIntelAsmWriter.inc:: $(TDFILES) $(TBLGEN)
	@echo "Building $(TARGET).td Intel assembly writer with tblgen"
	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-asm-writer -asmwriternum=1 -o $@

#$(TARGET)GenInstrSelector.inc:: $(TDFILES) $(TBLGEN)
#	@echo "Building $(TARGET).td instruction selector with tblgen"
#	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@

clean::
	$(VERB) rm -f *.inc
We know exactly what the value of $< is, so instead of using `basename $<` to get just the filename and not the full path, just use the filename directly. llvm-svn: 9730 2003-11-05 07:43:36 +01:00			`##===- lib/Target/X86/Makefile ------------------------------ Makefile --===##`
Added LLVM copyright notice to Makefiles. llvm-svn: 9312 2003-10-21 00:26:57 +02:00			`#`
			`# The LLVM Compiler Infrastructure`
			`#`
			`# This file was developed by the LLVM research group and is distributed under`
			`# the University of Illinois Open Source License. See LICENSE.TXT for details.`
			`#`
			`##===----------------------------------------------------------------------===##`
Initial checkin of X86 backend. We can instruction select exactly one instruction 'ret void'. Wow. llvm-svn: 4284 2002-10-26 00:55:53 +02:00			`LEVEL = ../../..`
			`LIBRARYNAME = x86`
			`include $(LEVEL)/Makefile.common`

Factor a bunch of the rules and add support for generating the asmwriter. llvm-svn: 15388 2004-08-01 08:01:32 +02:00			`TARGET = X86`

Switch over to TableGen generated register file description llvm-svn: 7511 2003-08-03 17:48:14 +02:00			`# Make sure that tblgen is run, first thing.`
Start using tablegenerated instruction descriptions llvm-svn: 7538 2003-08-03 23:54:59 +02:00			`$(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \`
			`X86GenRegisterInfo.inc X86GenInstrNames.inc \`
Add support for the -x86-asm-syntax flag, which can be used to choose between Intel and AT&T style assembly language. The ultimate goal of this is to eliminate the GasBugWorkaroundEmitter class, but for now AT&T style emission is not fully operational. llvm-svn: 16639 2004-10-03 22:36:57 +02:00			`X86GenInstrInfo.inc X86GenATTAsmWriter.inc \`
			`X86GenIntelAsmWriter.inc`
Factor a bunch of the rules and add support for generating the asmwriter. llvm-svn: 15388 2004-08-01 08:01:32 +02:00
			`TDFILES = $(SourceDir)/$(TARGET).td $(wildcard $(SourceDir)/*.td) \`
			`$(SourceDir)/../Target.td`
Switch over to TableGen generated register file description llvm-svn: 7511 2003-08-03 17:48:14 +02:00
Factor a bunch of the rules and add support for generating the asmwriter. llvm-svn: 15388 2004-08-01 08:01:32 +02:00			`$(TARGET)GenRegisterNames.inc:: $(TDFILES) $(TBLGEN)`
			`@echo "Building $(TARGET).td register names with tblgen"`
Be a little more specific about what is begin generated. Only print command line if VERBOSE=1 llvm-svn: 8453 2003-09-10 21:52:54 +02:00			`$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@`
Switch over to TableGen generated register file description llvm-svn: 7511 2003-08-03 17:48:14 +02:00
Factor a bunch of the rules and add support for generating the asmwriter. llvm-svn: 15388 2004-08-01 08:01:32 +02:00			`$(TARGET)GenRegisterInfo.h.inc:: $(TDFILES) $(TBLGEN)`
			`@echo "Building $(TARGET).td register information header with tblgen"`
Be a little more specific about what is begin generated. Only print command line if VERBOSE=1 llvm-svn: 8453 2003-09-10 21:52:54 +02:00			`$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@`
Switch over to TableGen generated register file description llvm-svn: 7511 2003-08-03 17:48:14 +02:00
Factor a bunch of the rules and add support for generating the asmwriter. llvm-svn: 15388 2004-08-01 08:01:32 +02:00			`$(TARGET)GenRegisterInfo.inc:: $(TDFILES) $(TBLGEN)`
			`@echo "Building $(TARGET).td register info implementation with tblgen"`
Be a little more specific about what is begin generated. Only print command line if VERBOSE=1 llvm-svn: 8453 2003-09-10 21:52:54 +02:00			`$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@`
Switch over to TableGen generated register file description llvm-svn: 7511 2003-08-03 17:48:14 +02:00
Factor a bunch of the rules and add support for generating the asmwriter. llvm-svn: 15388 2004-08-01 08:01:32 +02:00			`$(TARGET)GenInstrNames.inc:: $(TDFILES) $(TBLGEN)`
			`@echo "Building $(TARGET).td instruction names with tblgen"`
Be a little more specific about what is begin generated. Only print command line if VERBOSE=1 llvm-svn: 8453 2003-09-10 21:52:54 +02:00			`$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@`
Start using tablegenerated instruction descriptions llvm-svn: 7538 2003-08-03 23:54:59 +02:00
Factor a bunch of the rules and add support for generating the asmwriter. llvm-svn: 15388 2004-08-01 08:01:32 +02:00			`$(TARGET)GenInstrInfo.inc:: $(TDFILES) $(TBLGEN)`
			`@echo "Building $(TARGET).td instruction information with tblgen"`
Be a little more specific about what is begin generated. Only print command line if VERBOSE=1 llvm-svn: 8453 2003-09-10 21:52:54 +02:00			`$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@`
Add support for a pattern matching instruction selector. This is still in the early implementation phases, so it is disabled by default llvm-svn: 7719 2003-08-11 16:59:22 +02:00
Add support for the -x86-asm-syntax flag, which can be used to choose between Intel and AT&T style assembly language. The ultimate goal of this is to eliminate the GasBugWorkaroundEmitter class, but for now AT&T style emission is not fully operational. llvm-svn: 16639 2004-10-03 22:36:57 +02:00			`$(TARGET)GenATTAsmWriter.inc:: $(TDFILES) $(TBLGEN)`
			`@echo "Building $(TARGET).td AT&T assembly writer with tblgen"`
Factor a bunch of the rules and add support for generating the asmwriter. llvm-svn: 15388 2004-08-01 08:01:32 +02:00			`$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-asm-writer -o $@`
Tablgen files for really simple instruction selector llvm-svn: 12714 2004-04-06 21:34:00 +02:00
Add support for the -x86-asm-syntax flag, which can be used to choose between Intel and AT&T style assembly language. The ultimate goal of this is to eliminate the GasBugWorkaroundEmitter class, but for now AT&T style emission is not fully operational. llvm-svn: 16639 2004-10-03 22:36:57 +02:00			`$(TARGET)GenIntelAsmWriter.inc:: $(TDFILES) $(TBLGEN)`
			`@echo "Building $(TARGET).td Intel assembly writer with tblgen"`
			`$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-asm-writer -asmwriternum=1 -o $@`

Disable the pattern isel llvm-svn: 15787 2004-08-16 01:02:17 +02:00			`#$(TARGET)GenInstrSelector.inc:: $(TDFILES) $(TBLGEN)`
			`# @echo "Building $(TARGET).td instruction selector with tblgen"`
			`# $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@`
Tablgen files for really simple instruction selector llvm-svn: 12714 2004-04-06 21:34:00 +02:00
Switch over to TableGen generated register file description llvm-svn: 7511 2003-08-03 17:48:14 +02:00			`clean::`
			`$(VERB) rm -f *.inc`