llvm-mirror/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding2.ll

;PR15293: ARM codegen ice - expected larger existing stack allocation
;RUN: llc -mtriple=arm-linux-gnueabihf < %s | FileCheck %s

%struct4bytes = type { i32 }
%struct20bytes = type { i32, i32, i32, i32, i32 }

define void @foo(%struct4bytes* byval %p0, ; --> R0
                 %struct20bytes* byval %p1 ; --> R1,R2,R3, [SP+0 .. SP+8)
) {
;CHECK:  sub  sp, sp, #16
;CHECK:  push  {r11, lr}
;CHECK:  add  r12, sp, #8
;CHECK:  stm  r12, {r0, r1, r2, r3}
;CHECK:  add  r0, sp, #12
;CHECK:  bl  useInt
;CHECK:  pop  {r11, lr}
;CHECK:  add  sp, sp, #16

  %1 = ptrtoint %struct20bytes* %p1 to i32
  tail call void @useInt(i32 %1)
  ret void
}

declare void @useInt(i32)
PR15868 fix. Introduction: In case when stack alignment is 8 and GPRs parameter part size is not N8: we add padding to GPRs part, so part's last byte must be recovered at address K8-1. We need to do it, since remained (stack) part of parameter starts from address K8, and we need to "attach" "GPRs head" without gaps to it: Stack: \|---- 8 bytes block ----\| \|---- 8 bytes block ----\| \|---- 8 bytes... [ [padding] [GPRs head] ] [ ------ Tail passed via stack ------ ... FIX: Note, once we added padding we need to correct all* Arg offsets that are going after padded one. That's why we need this fix: Arg offsets were never corrected before this patch. See new test-cases included in patch. We also don't need to insert padding for byval parameters that are stored in GPRs only. We need pad only last byval parameter and only in case it outsides GPRs and stack alignment = 8. Though, stack area, allocated for recovered byval params, must satisfy "Size mod 8 = 0" restriction. This patch reduces stack usage for some cases: We can reduce ArgRegsSaveArea since inner N*4 bytes sized byval params my be "packed" with alignment 4 in some cases. llvm-svn: 182237 2013-05-20 10:01:34 +02:00			`;PR15293: ARM codegen ice - expected larger existing stack allocation`
			`;RUN: llc -mtriple=arm-linux-gnueabihf < %s \| FileCheck %s`

			`%struct4bytes = type { i32 }`
			`%struct20bytes = type { i32, i32, i32, i32, i32 }`

			`define void @foo(%struct4bytes* byval %p0, ; --> R0`
			`%struct20bytes* byval %p1 ; --> R1,R2,R3, [SP+0 .. SP+8)`
			`) {`
			`;CHECK: sub sp, sp, #16`
			`;CHECK: push {r11, lr}`
ARMLoadStoreOptimizer: Rewrite LDM/STM matching logic. This improves the logic in several ways and is a preparation for followup patches: - First perform an analysis and create a list of merge candidates, then transform. This simplifies the code in that you have don't have to care to much anymore that you may be holding iterators to MachineInstrs that get removed. - Analyze/Transform basic blocks in reverse order. This allows to use LivePhysRegs to find free registers instead of the RegisterScavenger. The RegisterScavenger will become less precise in the future as it relies on the deprecated kill-flags. - Return the newly created node in MergeOps so there's no need to look around in the schedule to find it. - Rename some MBBI iterators to InsertBefore to make their role clear. - General code cleanup. Differential Revision: http://reviews.llvm.org/D10140 llvm-svn: 241920 2015-07-10 20:08:49 +02:00			`;CHECK: add r12, sp, #8`
			`;CHECK: stm r12, {r0, r1, r2, r3}`
PR15868 fix. Introduction: In case when stack alignment is 8 and GPRs parameter part size is not N8: we add padding to GPRs part, so part's last byte must be recovered at address K8-1. We need to do it, since remained (stack) part of parameter starts from address K8, and we need to "attach" "GPRs head" without gaps to it: Stack: \|---- 8 bytes block ----\| \|---- 8 bytes block ----\| \|---- 8 bytes... [ [padding] [GPRs head] ] [ ------ Tail passed via stack ------ ... FIX: Note, once we added padding we need to correct all* Arg offsets that are going after padded one. That's why we need this fix: Arg offsets were never corrected before this patch. See new test-cases included in patch. We also don't need to insert padding for byval parameters that are stored in GPRs only. We need pad only last byval parameter and only in case it outsides GPRs and stack alignment = 8. Though, stack area, allocated for recovered byval params, must satisfy "Size mod 8 = 0" restriction. This patch reduces stack usage for some cases: We can reduce ArgRegsSaveArea since inner N*4 bytes sized byval params my be "packed" with alignment 4 in some cases. llvm-svn: 182237 2013-05-20 10:01:34 +02:00			`;CHECK: add r0, sp, #12`
			`;CHECK: bl useInt`
			`;CHECK: pop {r11, lr}`
			`;CHECK: add sp, sp, #16`

			`%1 = ptrtoint %struct20bytes* %p1 to i32`
			`tail call void @useInt(i32 %1)`
			`ret void`
			`}`

			`declare void @useInt(i32)`