2016-03-28 15:09:54 +02:00
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//===-- LanaiAsmPrinter.cpp - Lanai LLVM assembly writer ------------------===//
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//
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2019-01-19 09:50:56 +01:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2016-03-28 15:09:54 +02:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to the Lanai assembly language.
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//
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//===----------------------------------------------------------------------===//
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2019-05-11 03:25:58 +02:00
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#include "MCTargetDesc/LanaiInstPrinter.h"
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2019-06-03 19:02:07 +02:00
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#include "LanaiAluCode.h"
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#include "LanaiCondCode.h"
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2016-03-28 15:09:54 +02:00
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#include "LanaiInstrInfo.h"
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#include "LanaiMCInstLower.h"
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#include "LanaiTargetMachine.h"
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2019-05-15 01:17:18 +02:00
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#include "TargetInfo/LanaiTargetInfo.h"
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2016-03-28 15:09:54 +02:00
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Mangler.h"
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#include "llvm/IR/Module.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstBuilder.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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#define DEBUG_TYPE "asm-printer"
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using namespace llvm;
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namespace {
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class LanaiAsmPrinter : public AsmPrinter {
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public:
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explicit LanaiAsmPrinter(TargetMachine &TM,
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std::unique_ptr<MCStreamer> Streamer)
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: AsmPrinter(TM, std::move(Streamer)) {}
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2016-10-01 04:56:57 +02:00
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StringRef getPassName() const override { return "Lanai Assembly Printer"; }
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2016-03-28 15:09:54 +02:00
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2016-07-16 00:38:32 +02:00
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void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
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2016-03-28 15:09:54 +02:00
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bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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[AsmPrinter] refactor to remove remove AsmVariant. NFC
Summary:
The InlineAsm::AsmDialect is only required for X86; no architecture
makes use of it and as such it gets passed around between arch-specific
and general code while being unused for all architectures but X86.
Since the AsmDialect is queried from a MachineInstr, which we also pass
around, remove the additional AsmDialect parameter and query for it deep
in the X86AsmPrinter only when needed/as late as possible.
This refactor should help later planned refactors to AsmPrinter, as this
difference in the X86AsmPrinter makes it harder to make AsmPrinter more
generic.
Reviewers: craig.topper
Subscribers: jholewinski, arsenm, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, javed.absar, sbc100, jgravelle-google, eraman, hiraditya, aheejin, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, llvm-commits, peter.smith, srhines
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60488
llvm-svn: 358101
2019-04-10 18:38:43 +02:00
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const char *ExtraCode, raw_ostream &O) override;
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2020-02-14 06:58:16 +01:00
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void emitInstruction(const MachineInstr *MI) override;
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2016-03-28 15:09:54 +02:00
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bool isBlockOnlyReachableByFallthrough(
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const MachineBasicBlock *MBB) const override;
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private:
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void customEmitInstruction(const MachineInstr *MI);
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void emitCallInstruction(const MachineInstr *MI);
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};
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} // end of anonymous namespace
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void LanaiAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
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2016-07-16 00:38:32 +02:00
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raw_ostream &O) {
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2016-03-28 15:09:54 +02:00
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const MachineOperand &MO = MI->getOperand(OpNum);
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switch (MO.getType()) {
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case MachineOperand::MO_Register:
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O << LanaiInstPrinter::getRegisterName(MO.getReg());
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break;
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case MachineOperand::MO_Immediate:
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O << MO.getImm();
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break;
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case MachineOperand::MO_MachineBasicBlock:
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O << *MO.getMBB()->getSymbol();
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break;
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case MachineOperand::MO_GlobalAddress:
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2016-07-08 01:36:04 +02:00
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O << *getSymbol(MO.getGlobal());
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2016-03-28 15:09:54 +02:00
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break;
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case MachineOperand::MO_BlockAddress: {
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MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress());
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O << BA->getName();
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break;
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}
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case MachineOperand::MO_ExternalSymbol:
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2016-07-08 01:36:04 +02:00
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O << *GetExternalSymbolSymbol(MO.getSymbolName());
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2016-03-28 15:09:54 +02:00
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break;
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case MachineOperand::MO_JumpTableIndex:
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O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() << '_'
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<< MO.getIndex();
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << '_'
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<< MO.getIndex();
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return;
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default:
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llvm_unreachable("<unknown operand type>");
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}
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}
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// PrintAsmOperand - Print out an operand for an inline asm expression.
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bool LanaiAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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const char *ExtraCode, raw_ostream &O) {
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// Does this asm operand have a single letter operand modifier?
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if (ExtraCode && ExtraCode[0]) {
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if (ExtraCode[1])
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return true; // Unknown modifier.
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switch (ExtraCode[0]) {
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// The highest-numbered register of a pair.
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case 'H': {
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if (OpNo == 0)
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return true;
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const MachineOperand &FlagsOP = MI->getOperand(OpNo - 1);
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if (!FlagsOP.isImm())
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return true;
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unsigned Flags = FlagsOP.getImm();
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unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
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if (NumVals != 2)
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return true;
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unsigned RegOp = OpNo + 1;
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if (RegOp >= MI->getNumOperands())
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return true;
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const MachineOperand &MO = MI->getOperand(RegOp);
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if (!MO.isReg())
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return true;
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Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).
Partial reverts in:
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&
MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register
PPCFastISel.cpp - No Register::operator-=()
PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&
MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor
Manual fixups in:
ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned&
HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register
HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.
PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned&
Depends on D65919
Reviewers: arsenm, bogner, craig.topper, RKSimon
Reviewed By: arsenm
Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65962
llvm-svn: 369041
2019-08-15 21:22:08 +02:00
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Register Reg = MO.getReg();
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2016-03-28 15:09:54 +02:00
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O << LanaiInstPrinter::getRegisterName(Reg);
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return false;
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}
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default:
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[AsmPrinter] refactor to support %c w/ GlobalAddress'
Summary:
Targets like ARM, MSP430, PPC, and SystemZ have complex behavior when
printing the address of a MachineOperand::MO_GlobalAddress. Move that
handling into a new overriden method in each base class. A virtual
method was added to the base class for handling the generic case.
Refactors a few subclasses to support the target independent %a, %c, and
%n.
The patch also contains small cleanups for AVRAsmPrinter and
SystemZAsmPrinter.
It seems that NVPTXTargetLowering is possibly missing some logic to
transform GlobalAddressSDNodes for
TargetLowering::LowerAsmOperandForConstraint to handle with "i" extended
inline assembly asm constraints.
Fixes:
- https://bugs.llvm.org/show_bug.cgi?id=41402
- https://github.com/ClangBuiltLinux/linux/issues/449
Reviewers: echristo, void
Reviewed By: void
Subscribers: void, craig.topper, jholewinski, dschuff, jyknight, dylanmckay, sdardis, nemanjai, javed.absar, sbc100, jgravelle-google, eraman, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, jrtc27, atanasyan, jsji, llvm-commits, kees, tpimh, nathanchance, peter.smith, srhines
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60887
llvm-svn: 359337
2019-04-26 20:45:04 +02:00
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return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, O);
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2016-03-28 15:09:54 +02:00
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}
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}
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printOperand(MI, OpNo, O);
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return false;
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}
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//===----------------------------------------------------------------------===//
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void LanaiAsmPrinter::emitCallInstruction(const MachineInstr *MI) {
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assert((MI->getOpcode() == Lanai::CALL || MI->getOpcode() == Lanai::CALLR) &&
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"Unsupported call function");
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2016-09-16 19:07:23 +02:00
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LanaiMCInstLower MCInstLowering(OutContext, *this);
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2016-03-28 15:09:54 +02:00
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MCSubtargetInfo STI = getSubtargetInfo();
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// Insert save rca instruction immediately before the call.
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// TODO: We should generate a pc-relative mov instruction here instead
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// of pc + 16 (should be mov .+16 %rca).
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2020-02-14 06:58:16 +01:00
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OutStreamer->emitInstruction(MCInstBuilder(Lanai::ADD_I_LO)
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2016-03-28 15:09:54 +02:00
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.addReg(Lanai::RCA)
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.addReg(Lanai::PC)
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.addImm(16),
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STI);
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// Push rca onto the stack.
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// st %rca, [--%sp]
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2020-02-14 06:58:16 +01:00
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OutStreamer->emitInstruction(MCInstBuilder(Lanai::SW_RI)
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2016-03-28 15:09:54 +02:00
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.addReg(Lanai::RCA)
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.addReg(Lanai::SP)
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.addImm(-4)
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.addImm(LPAC::makePreOp(LPAC::ADD)),
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STI);
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// Lower the call instruction.
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if (MI->getOpcode() == Lanai::CALL) {
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MCInst TmpInst;
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MCInstLowering.Lower(MI, TmpInst);
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TmpInst.setOpcode(Lanai::BT);
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2020-02-14 06:58:16 +01:00
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OutStreamer->emitInstruction(TmpInst, STI);
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2016-03-28 15:09:54 +02:00
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} else {
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2020-02-14 06:58:16 +01:00
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OutStreamer->emitInstruction(MCInstBuilder(Lanai::ADD_R)
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2016-03-28 15:09:54 +02:00
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.addReg(Lanai::PC)
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.addReg(MI->getOperand(0).getReg())
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.addReg(Lanai::R0)
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.addImm(LPCC::ICC_T),
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STI);
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}
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}
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void LanaiAsmPrinter::customEmitInstruction(const MachineInstr *MI) {
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2016-09-16 19:07:23 +02:00
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LanaiMCInstLower MCInstLowering(OutContext, *this);
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2016-03-28 15:09:54 +02:00
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MCSubtargetInfo STI = getSubtargetInfo();
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MCInst TmpInst;
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MCInstLowering.Lower(MI, TmpInst);
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2020-02-14 06:58:16 +01:00
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OutStreamer->emitInstruction(TmpInst, STI);
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2016-03-28 15:09:54 +02:00
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}
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2020-02-14 06:58:16 +01:00
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void LanaiAsmPrinter::emitInstruction(const MachineInstr *MI) {
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2016-03-28 15:09:54 +02:00
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MachineBasicBlock::const_instr_iterator I = MI->getIterator();
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MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
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do {
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if (I->isCall()) {
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emitCallInstruction(&*I);
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continue;
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}
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customEmitInstruction(&*I);
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} while ((++I != E) && I->isInsideBundle());
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}
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// isBlockOnlyReachableByFallthough - Return true if the basic block has
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// exactly one predecessor and the control transfer mechanism between
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// the predecessor and this block is a fall-through.
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2020-01-21 16:47:35 +01:00
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// FIXME: could the overridden cases be handled in analyzeBranch?
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2016-03-28 15:09:54 +02:00
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bool LanaiAsmPrinter::isBlockOnlyReachableByFallthrough(
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const MachineBasicBlock *MBB) const {
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// The predecessor has to be immediately before this block.
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const MachineBasicBlock *Pred = *MBB->pred_begin();
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// If the predecessor is a switch statement, assume a jump table
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// implementation, so it is not a fall through.
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if (const BasicBlock *B = Pred->getBasicBlock())
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if (isa<SwitchInst>(B->getTerminator()))
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return false;
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// Check default implementation
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if (!AsmPrinter::isBlockOnlyReachableByFallthrough(MBB))
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return false;
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// Otherwise, check the last instruction.
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// Check if the last terminator is an unconditional branch.
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MachineBasicBlock::const_iterator I = Pred->end();
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while (I != Pred->begin() && !(--I)->isTerminator()) {
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}
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return !I->isBarrier();
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}
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// Force static initialization.
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CMake: Make most target symbols hidden by default
Summary:
For builds with LLVM_BUILD_LLVM_DYLIB=ON and BUILD_SHARED_LIBS=OFF
this change makes all symbols in the target specific libraries hidden
by default.
A new macro called LLVM_EXTERNAL_VISIBILITY has been added to mark symbols in these
libraries public, which is mainly needed for the definitions of the
LLVMInitialize* functions.
This patch reduces the number of public symbols in libLLVM.so by about
25%. This should improve load times for the dynamic library and also
make abi checker tools, like abidiff require less memory when analyzing
libLLVM.so
One side-effect of this change is that for builds with
LLVM_BUILD_LLVM_DYLIB=ON and LLVM_LINK_LLVM_DYLIB=ON some unittests that
access symbols that are no longer public will need to be statically linked.
Before and after public symbol counts (using gcc 8.2.1, ld.bfd 2.31.1):
nm before/libLLVM-9svn.so | grep ' [A-Zuvw] ' | wc -l
36221
nm after/libLLVM-9svn.so | grep ' [A-Zuvw] ' | wc -l
26278
Reviewers: chandlerc, beanz, mgorny, rnk, hans
Reviewed By: rnk, hans
Subscribers: merge_guards_bot, luismarques, smeenai, ldionne, lenary, s.egerton, pzheng, sameer.abuasal, MaskRay, wuzish, echristo, Jim, hiraditya, michaelplatings, chapuni, jholewinski, arsenm, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, javed.absar, sbc100, jgravelle-google, aheejin, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, mgrang, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, kristina, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D54439
2020-01-15 04:15:07 +01:00
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLanaiAsmPrinter() {
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2016-10-10 01:00:34 +02:00
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RegisterAsmPrinter<LanaiAsmPrinter> X(getTheLanaiTarget());
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2016-03-28 15:09:54 +02:00
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}
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