1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 03:02:36 +01:00
llvm-mirror/test/CodeGen/AMDGPU/subreg-intervals.mir

49 lines
908 B
Plaintext
Raw Normal View History

# RUN: llc -march=amdgcn -run-pass liveintervals -debug-only=regalloc -o /dev/null %s 2>&1 | FileCheck %s
# REQUIRES: asserts
# CHECK: INTERVALS
# CHECK: %0
# CHECK-LABEL: Machine code for function test0:
# CHECK: INTERVALS
# CHECK: %0
# CHECK-LABEL: Machine code for function test1:
--- |
define amdgpu_kernel void @test0() { ret void }
define amdgpu_kernel void @test1() { ret void }
...
---
name: test0
registers:
- { id: 0, class: sreg_64 }
body: |
bb.0:
S_NOP 0, implicit-def %0
S_NOP 0, implicit %0
S_NOP 0, implicit-def undef %0.sub0
S_NOP 0, implicit %0
...
---
name: test1
registers:
- { id: 0, class: sreg_64 }
body: |
bb.0:
S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
S_BRANCH %bb.2
bb.1:
S_NOP 0, implicit-def undef %0.sub0
S_BRANCH %bb.3
bb.2:
S_NOP 0, implicit-def %0
S_BRANCH %bb.3
bb.3:
S_NOP 0
S_NOP 0, implicit %0
...