2012-12-11 22:25:42 +01:00
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//===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Parent TargetRegisterInfo class common to all hw codegen targets.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPURegisterInfo.h"
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#include "AMDGPUTargetMachine.h"
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using namespace llvm;
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2014-06-13 03:32:00 +02:00
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AMDGPURegisterInfo::AMDGPURegisterInfo(const AMDGPUSubtarget &st)
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2012-12-11 22:25:42 +01:00
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: AMDGPUGenRegisterInfo(0),
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2014-06-13 03:32:00 +02:00
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ST(st)
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2012-12-11 22:25:42 +01:00
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{ }
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//===----------------------------------------------------------------------===//
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// Function handling callbacks - Functions are a seldom used feature of GPUS, so
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// they are not supported at this time.
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//===----------------------------------------------------------------------===//
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2014-04-04 07:16:06 +02:00
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const MCPhysReg AMDGPURegisterInfo::CalleeSavedReg = AMDGPU::NoRegister;
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2012-12-11 22:25:42 +01:00
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2014-04-04 07:16:06 +02:00
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const MCPhysReg*
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AMDGPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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2012-12-11 22:25:42 +01:00
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return &CalleeSavedReg;
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}
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void AMDGPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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int SPAdj,
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2013-01-31 23:55:51 +01:00
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unsigned FIOperandNum,
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2012-12-11 22:25:42 +01:00
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RegScavenger *RS) const {
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2013-12-10 22:37:42 +01:00
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llvm_unreachable("Subroutines not supported yet");
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2012-12-11 22:25:42 +01:00
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}
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unsigned AMDGPURegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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2014-12-03 05:08:00 +01:00
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return AMDGPU::NoRegister;
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2012-12-11 22:25:42 +01:00
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}
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2013-08-15 01:24:32 +02:00
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unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) const {
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static const unsigned SubRegs[] = {
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AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4,
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AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9,
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AMDGPU::sub10, AMDGPU::sub11, AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14,
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AMDGPU::sub15
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};
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2014-05-15 23:44:05 +02:00
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assert(Channel < array_lengthof(SubRegs));
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2013-08-15 01:24:32 +02:00
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return SubRegs[Channel];
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}
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2013-02-06 18:32:29 +01:00
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unsigned AMDGPURegisterInfo::getIndirectSubReg(unsigned IndirectIndex) const {
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2013-08-15 01:24:32 +02:00
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return getSubRegFromChannel(IndirectIndex);
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2013-02-06 18:32:29 +01:00
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}
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2012-12-11 22:25:42 +01:00
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#define GET_REGINFO_TARGET_DESC
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#include "AMDGPUGenRegisterInfo.inc"
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