RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-26 12:43:36 +01:00
Code Issues Projects Releases Wiki Activity
2b8eaac9b5
llvm-mirror/test/CodeGen/WebAssembly/vector-sdiv.ll

24 lines
774 B
LLVM
Raw Normal View History

[DAGCombiner] Fix a case of 1 in non-splat vector pow2 divisor Summary: D42479 (rL329525) enabled SDIV combine for pow2 non-splat vector dividers. But when there is a 1 in a vector, the instruction sequence to be generated involves shifting a value by the number of its bit widths, which is undefined (https://github.com/llvm-mirror/llvm/blob/c64f4dbfe31e509f9c1092b951e524b056245af8/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L6000-L6006). Especially, in architectures that do not support vector instructions, each of element in a vector will be computed separately using scalar operations, and then the resulting value will be undef for '1' values in a vector. (All 1's vector is fine; only vectors mixed with 1 and others will be affected.) Reviewers: RKSimon, jgravelle-google Subscribers: jfb, dschuff, sbc100, jgravelle-google, llvm-commits Differential Revision: https://reviews.llvm.org/D46161 llvm-svn: 331092
2018-04-28 00:23:11 +02:00
; RUN: llc < %s -asm-verbose=false -fast-isel=false -disable-wasm-fallthrough-return-opt | FileCheck %s
[WebAssembly] Convert remaining tests from elf to wasm output format Differential Revision: https://reviews.llvm.org/D48748 llvm-svn: 336116
2018-07-02 18:03:49 +02:00
target triple = "wasm32-unknown-unknown"
[DAGCombiner] Fix a case of 1 in non-splat vector pow2 divisor Summary: D42479 (rL329525) enabled SDIV combine for pow2 non-splat vector dividers. But when there is a 1 in a vector, the instruction sequence to be generated involves shifting a value by the number of its bit widths, which is undefined (https://github.com/llvm-mirror/llvm/blob/c64f4dbfe31e509f9c1092b951e524b056245af8/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L6000-L6006). Especially, in architectures that do not support vector instructions, each of element in a vector will be computed separately using scalar operations, and then the resulting value will be undef for '1' values in a vector. (All 1's vector is fine; only vectors mixed with 1 and others will be affected.) Reviewers: RKSimon, jgravelle-google Subscribers: jfb, dschuff, sbc100, jgravelle-google, llvm-commits Differential Revision: https://reviews.llvm.org/D46161 llvm-svn: 331092
2018-04-28 00:23:11 +02:00
[WebAssembly] Update comments for non-splat pow2 vector test case Summary: After rL335727, (sdiv X, 1) is treated as a special case, so we can safely transform 'sdiv's in non-splat pow vectors into 'shr's even when some of its entries are '1'. The test expectations have been already fixed in rL335771, but the comments were out of date. Also changed the filename from `vector_sdiv.ll` to `vector-sdiv.ll` to be consistent with other test file names. Reviewers: RKSimon Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D48692 llvm-svn: 336018
2018-06-29 23:27:20 +02:00
; This should be treated as a non-splat vector of pow2 divisor, so sdivs will be
; transformed to shrs in DAGCombiner. There will be 4 stores and 3 shrs (For '1'
; entry we don't need a shr).
[DAGCombiner] Fix a case of 1 in non-splat vector pow2 divisor Summary: D42479 (rL329525) enabled SDIV combine for pow2 non-splat vector dividers. But when there is a 1 in a vector, the instruction sequence to be generated involves shifting a value by the number of its bit widths, which is undefined (https://github.com/llvm-mirror/llvm/blob/c64f4dbfe31e509f9c1092b951e524b056245af8/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L6000-L6006). Especially, in architectures that do not support vector instructions, each of element in a vector will be computed separately using scalar operations, and then the resulting value will be undef for '1' values in a vector. (All 1's vector is fine; only vectors mixed with 1 and others will be affected.) Reviewers: RKSimon, jgravelle-google Subscribers: jfb, dschuff, sbc100, jgravelle-google, llvm-commits Differential Revision: https://reviews.llvm.org/D46161 llvm-svn: 331092
2018-04-28 00:23:11 +02:00
; CHECK-LABEL: vector_sdiv:
; CHECK-DAG: i32.store
[WebAssembly] Try fixing test/CodeGen/WebAssembly/vector_sdiv.ll llvm-svn: 335771
2018-06-27 21:35:50 +02:00
; CHECK-DAG: i32.shr_u
[DAGCombiner] Fix a case of 1 in non-splat vector pow2 divisor Summary: D42479 (rL329525) enabled SDIV combine for pow2 non-splat vector dividers. But when there is a 1 in a vector, the instruction sequence to be generated involves shifting a value by the number of its bit widths, which is undefined (https://github.com/llvm-mirror/llvm/blob/c64f4dbfe31e509f9c1092b951e524b056245af8/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L6000-L6006). Especially, in architectures that do not support vector instructions, each of element in a vector will be computed separately using scalar operations, and then the resulting value will be undef for '1' values in a vector. (All 1's vector is fine; only vectors mixed with 1 and others will be affected.) Reviewers: RKSimon, jgravelle-google Subscribers: jfb, dschuff, sbc100, jgravelle-google, llvm-commits Differential Revision: https://reviews.llvm.org/D46161 llvm-svn: 331092
2018-04-28 00:23:11 +02:00
; CHECK-DAG: i32.store
[WebAssembly] Try fixing test/CodeGen/WebAssembly/vector_sdiv.ll llvm-svn: 335771
2018-06-27 21:35:50 +02:00
; CHECK-DAG: i32.shr_u
[DAGCombiner] Fix a case of 1 in non-splat vector pow2 divisor Summary: D42479 (rL329525) enabled SDIV combine for pow2 non-splat vector dividers. But when there is a 1 in a vector, the instruction sequence to be generated involves shifting a value by the number of its bit widths, which is undefined (https://github.com/llvm-mirror/llvm/blob/c64f4dbfe31e509f9c1092b951e524b056245af8/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L6000-L6006). Especially, in architectures that do not support vector instructions, each of element in a vector will be computed separately using scalar operations, and then the resulting value will be undef for '1' values in a vector. (All 1's vector is fine; only vectors mixed with 1 and others will be affected.) Reviewers: RKSimon, jgravelle-google Subscribers: jfb, dschuff, sbc100, jgravelle-google, llvm-commits Differential Revision: https://reviews.llvm.org/D46161 llvm-svn: 331092
2018-04-28 00:23:11 +02:00
; CHECK-DAG: i32.store
[WebAssembly] Try fixing test/CodeGen/WebAssembly/vector_sdiv.ll llvm-svn: 335771
2018-06-27 21:35:50 +02:00
; CHECK-DAG: i32.shr_u
[DAGCombiner] Fix a case of 1 in non-splat vector pow2 divisor Summary: D42479 (rL329525) enabled SDIV combine for pow2 non-splat vector dividers. But when there is a 1 in a vector, the instruction sequence to be generated involves shifting a value by the number of its bit widths, which is undefined (https://github.com/llvm-mirror/llvm/blob/c64f4dbfe31e509f9c1092b951e524b056245af8/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L6000-L6006). Especially, in architectures that do not support vector instructions, each of element in a vector will be computed separately using scalar operations, and then the resulting value will be undef for '1' values in a vector. (All 1's vector is fine; only vectors mixed with 1 and others will be affected.) Reviewers: RKSimon, jgravelle-google Subscribers: jfb, dschuff, sbc100, jgravelle-google, llvm-commits Differential Revision: https://reviews.llvm.org/D46161 llvm-svn: 331092
2018-04-28 00:23:11 +02:00
; CHECK-DAG: i32.store
define void @vector_sdiv(<4 x i32>* %x, <4 x i32>* readonly %y) {
entry:
%0 = load <4 x i32>, <4 x i32>* %y, align 16
%div = sdiv <4 x i32> %0, <i32 1, i32 4, i32 2, i32 8>
store <4 x i32> %div, <4 x i32>* %x, align 16
ret void
}
Reference in New Issue Copy Permalink