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llvm-mirror/test/MC/AArch64/armv8.5a-rand-error.s

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[AArch64][v8.5A] Add Armv8.5-A random number instructions This adds two new system registers, used to generate random numbers. This is an optional extension to v8.5-A, and will be controlled by the "+rng" modifier of the -march= and -mcpu= options. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52481 llvm-svn: 343217
2018-09-27 14:01:40 +00:00
// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+rand < %s 2>&1| FileCheck %s
mrs rndr
mrs rndrrs
// CHECK: invalid operand for instruction
// CHECK-NEXT: rndr
// CHECK: invalid operand for instruction
// CHECK-NEXT: rndrrs
mrs rndr, x0
mrs rndrrs, x1
// CHECK: invalid operand for instruction
// CHECK-NEXT: rndr
// CHECK: invalid operand for instruction
// CHECK-NEXT: rndrrs
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