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llvm-mirror/test/CodeGen/AArch64/arm64-register-pairing.ll

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ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
; RUN: llc -mtriple=arm64-apple-ios < %s | FileCheck %s
[AArch64] Reduce number of callee-save save/restores. Summary: Before this change, callee-save registers would be rounded up to even pairs of GPRs and FPRs. This change eliminates these extra padding load/stores, though it does keep the stack allocation the same size unless both the GPR and FPR sets have an odd size, in which case one full pair stack slot (16 bytes) is saved. This optimization cannot currently be done for MachO targets since they rely on a fast-path .debug_frame equivalent that can only encode callee-save registers as pairs. Reviewers: t.p.northover, rengolin, mcrosier, jmolloy Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17000 llvm-svn: 260689
2016-02-12 17:31:41 +01:00
; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck -check-prefix CHECK-NOTMACHO %s
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
;
; rdar://14075006
define void @odd() nounwind {
; CHECK-LABEL: odd:
; CHECK: stp d15, d14, [sp, #-144]!
; CHECK: stp d13, d12, [sp, #16]
; CHECK: stp d11, d10, [sp, #32]
; CHECK: stp d9, d8, [sp, #48]
; CHECK: stp x28, x27, [sp, #64]
; CHECK: stp x26, x25, [sp, #80]
; CHECK: stp x24, x23, [sp, #96]
; CHECK: stp x22, x21, [sp, #112]
; CHECK: stp x20, x19, [sp, #128]
AArch64: allow MOV (imm) alias to be printed The backend has been around for years, it's pretty ridiculous that we can't even use the preferred form for printing "MOV" aliases. Unfortunately, TableGen can't handle the complex predicates when printing so it's a bunch of nasty C++. Oh well. llvm-svn: 272865
2016-06-16 03:42:25 +02:00
; CHECK: mov x0, #42
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
; CHECK: ldp x20, x19, [sp, #128]
; CHECK: ldp x22, x21, [sp, #112]
; CHECK: ldp x24, x23, [sp, #96]
; CHECK: ldp x26, x25, [sp, #80]
; CHECK: ldp x28, x27, [sp, #64]
; CHECK: ldp d9, d8, [sp, #48]
; CHECK: ldp d11, d10, [sp, #32]
; CHECK: ldp d13, d12, [sp, #16]
; CHECK: ldp d15, d14, [sp], #144
[AArch64] Reduce number of callee-save save/restores. Summary: Before this change, callee-save registers would be rounded up to even pairs of GPRs and FPRs. This change eliminates these extra padding load/stores, though it does keep the stack allocation the same size unless both the GPR and FPR sets have an odd size, in which case one full pair stack slot (16 bytes) is saved. This optimization cannot currently be done for MachO targets since they rely on a fast-path .debug_frame equivalent that can only encode callee-save registers as pairs. Reviewers: t.p.northover, rengolin, mcrosier, jmolloy Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17000 llvm-svn: 260689
2016-02-12 17:31:41 +01:00
; CHECK-NOTMACHO-LABEL: odd:
; CHECK-NOTMACHO: stp d14, d12, [sp, #-80]!
; CHECK-NOTMACHO: stp d10, d8, [sp, #16]
; CHECK-NOTMACHO: str x27, [sp, #32]
; CHECK-NOTMACHO: stp x25, x23, [sp, #48]
; CHECK-NOTMACHO: stp x21, x19, [sp, #64]
AArch64: allow MOV (imm) alias to be printed The backend has been around for years, it's pretty ridiculous that we can't even use the preferred form for printing "MOV" aliases. Unfortunately, TableGen can't handle the complex predicates when printing so it's a bunch of nasty C++. Oh well. llvm-svn: 272865
2016-06-16 03:42:25 +02:00
; CHECK-NOTMACHO: mov x0, #42
[AArch64] Reduce number of callee-save save/restores. Summary: Before this change, callee-save registers would be rounded up to even pairs of GPRs and FPRs. This change eliminates these extra padding load/stores, though it does keep the stack allocation the same size unless both the GPR and FPR sets have an odd size, in which case one full pair stack slot (16 bytes) is saved. This optimization cannot currently be done for MachO targets since they rely on a fast-path .debug_frame equivalent that can only encode callee-save registers as pairs. Reviewers: t.p.northover, rengolin, mcrosier, jmolloy Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17000 llvm-svn: 260689
2016-02-12 17:31:41 +01:00
; CHECK-NOTMACHO: ldp x21, x19, [sp, #64]
; CHECK-NOTMACHO: ldp x25, x23, [sp, #48]
; CHECK-NOTMACHO: ldr x27, [sp, #32]
; CHECK-NOTMACHO: ldp d10, d8, [sp, #16]
; CHECK-NOTMACHO: ldp d14, d12, [sp], #80
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
call void asm sideeffect "mov x0, #42", "~{x0},~{x19},~{x21},~{x23},~{x25},~{x27},~{d8},~{d10},~{d12},~{d14}"() nounwind
ret void
}
define void @even() nounwind {
; CHECK-LABEL: even:
; CHECK: stp d15, d14, [sp, #-144]!
; CHECK: stp d13, d12, [sp, #16]
; CHECK: stp d11, d10, [sp, #32]
; CHECK: stp d9, d8, [sp, #48]
; CHECK: stp x28, x27, [sp, #64]
; CHECK: stp x26, x25, [sp, #80]
; CHECK: stp x24, x23, [sp, #96]
; CHECK: stp x22, x21, [sp, #112]
; CHECK: stp x20, x19, [sp, #128]
AArch64: allow MOV (imm) alias to be printed The backend has been around for years, it's pretty ridiculous that we can't even use the preferred form for printing "MOV" aliases. Unfortunately, TableGen can't handle the complex predicates when printing so it's a bunch of nasty C++. Oh well. llvm-svn: 272865
2016-06-16 03:42:25 +02:00
; CHECK: mov x0, #42
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
; CHECK: ldp x20, x19, [sp, #128]
; CHECK: ldp x22, x21, [sp, #112]
; CHECK: ldp x24, x23, [sp, #96]
; CHECK: ldp x26, x25, [sp, #80]
; CHECK: ldp x28, x27, [sp, #64]
; CHECK: ldp d9, d8, [sp, #48]
; CHECK: ldp d11, d10, [sp, #32]
; CHECK: ldp d13, d12, [sp, #16]
; CHECK: ldp d15, d14, [sp], #144
[AArch64] Reduce number of callee-save save/restores. Summary: Before this change, callee-save registers would be rounded up to even pairs of GPRs and FPRs. This change eliminates these extra padding load/stores, though it does keep the stack allocation the same size unless both the GPR and FPR sets have an odd size, in which case one full pair stack slot (16 bytes) is saved. This optimization cannot currently be done for MachO targets since they rely on a fast-path .debug_frame equivalent that can only encode callee-save registers as pairs. Reviewers: t.p.northover, rengolin, mcrosier, jmolloy Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17000 llvm-svn: 260689
2016-02-12 17:31:41 +01:00
; CHECK-NOTMACHO-LABEL: even:
; CHECK-NOTMACHO: stp d15, d13, [sp, #-80]!
; CHECK-NOTMACHO: stp d11, d9, [sp, #16]
; CHECK-NOTMACHO: str x28, [sp, #32]
; CHECK-NOTMACHO: stp x26, x24, [sp, #48]
; CHECK-NOTMACHO: stp x22, x20, [sp, #64]
AArch64: allow MOV (imm) alias to be printed The backend has been around for years, it's pretty ridiculous that we can't even use the preferred form for printing "MOV" aliases. Unfortunately, TableGen can't handle the complex predicates when printing so it's a bunch of nasty C++. Oh well. llvm-svn: 272865
2016-06-16 03:42:25 +02:00
; CHECK-NOTMACHO: mov x0, #42
[AArch64] Reduce number of callee-save save/restores. Summary: Before this change, callee-save registers would be rounded up to even pairs of GPRs and FPRs. This change eliminates these extra padding load/stores, though it does keep the stack allocation the same size unless both the GPR and FPR sets have an odd size, in which case one full pair stack slot (16 bytes) is saved. This optimization cannot currently be done for MachO targets since they rely on a fast-path .debug_frame equivalent that can only encode callee-save registers as pairs. Reviewers: t.p.northover, rengolin, mcrosier, jmolloy Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17000 llvm-svn: 260689
2016-02-12 17:31:41 +01:00
; CHECK-NOTMACHO: ldp x22, x20, [sp, #64]
; CHECK-NOTMACHO: ldp x26, x24, [sp, #48]
; CHECK-NOTMACHO: ldr x28, [sp, #32]
; CHECK-NOTMACHO: ldp d11, d9, [sp, #16]
; CHECK-NOTMACHO: ldp d15, d13, [sp], #80
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
call void asm sideeffect "mov x0, #42", "~{x0},~{x20},~{x22},~{x24},~{x26},~{x28},~{d9},~{d11},~{d13},~{d15}"() nounwind
ret void
}
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