llvm-mirror/test/CodeGen/Mips/named-register-n32.ll

; RUN: llc -march=mips64 -relocation-model=static -mattr=+noabicalls -target-abi n32 < %s | FileCheck %s

define i32* @get_gp() {
entry:
  %0 = call i64 @llvm.read_register.i64(metadata !0)
  %1 = trunc i64 %0 to i32
  %2 = inttoptr i32 %1 to i32*
  ret i32* %2
}

; CHECK-LABEL: get_gp:
; CHECK:           sll $2, $gp, 0

declare i64 @llvm.read_register.i64(metadata)

!llvm.named.register.$28 = !{!0}

!0 = !{!"$28"}
Move the Mips target to storing the ABI in the TargetMachine rather than on MipsSubtargetInfo. This required a bit of massaging in the MC level to handle this since MC is a) largely a collection of disparate classes with no hierarchy, and b) there's no overarching equivalent to the TargetMachine, instead only the subtarget via MCSubtargetInfo (which is the base class of TargetSubtargetInfo). We're now storing the ABI in both the TargetMachine level and in the MC level because the AsmParser and the TargetStreamer both need to know what ABI we have to parse assembly and emit objects. The target streamer has a pointer to the one in the asm parser and is updated when the asm parser is created. This is fragile as the FIXME comment notes, but shouldn't be a problem in practice since we always create an asm parser before attempting to emit object code via the assembler. The TargetMachine now contains the ABI so that the DataLayout can be constructed dependent upon ABI. All testcases have been updated to use the -target-abi command line flag so that we can set the ABI without using a subtarget feature. Should be no change visible externally here. llvm-svn: 227102 2015-01-26 18:33:46 +01:00			`; RUN: llc -march=mips64 -relocation-model=static -mattr=+noabicalls -target-abi n32 < %s \| FileCheck %s`
[mips] Add support for accessing $gp as a named register. Summary: Mips Linux uses $gp to hold a pointer to thread info structure and accesses it with a named register. This makes this work for LLVM. The N32 ABI doesn't quite work yet since the frontend generates incorrect IR for this case. It neglects to truncate the 64-bit GPR to a 32-bit value before converting to a pointer. Given correct IR (as in the testcase in this patch), it works correctly. Reviewers: sstankovic, vmedic, atanasyan Reviewed By: atanasyan Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6893 llvm-svn: 225529 2015-01-09 18:21:30 +01:00
			`define i32* @get_gp() {`
			`entry:`
			`%0 = call i64 @llvm.read_register.i64(metadata !0)`
			`%1 = trunc i64 %0 to i32`
			`%2 = inttoptr i32 %1 to i32*`
			`ret i32* %2`
			`}`

			`; CHECK-LABEL: get_gp:`
			`; CHECK: sll $2, $gp, 0`

			`declare i64 @llvm.read_register.i64(metadata)`

			`!llvm.named.register.$28 = !{!0}`

			`!0 = !{!"$28"}`