2012-02-28 08:46:26 +01:00
|
|
|
//===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
|
2007-06-06 09:42:06 +02:00
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
2007-12-29 21:36:04 +01:00
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
2007-06-06 09:42:06 +02:00
|
|
|
//
|
2011-04-15 23:51:11 +02:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-08-18 04:18:07 +02:00
|
|
|
// This is the top level entry point for the Mips target.
|
2011-04-15 23:51:11 +02:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 09:42:06 +02:00
|
|
|
|
2011-04-15 23:51:11 +02:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-08-18 04:18:07 +02:00
|
|
|
// Target-independent interfaces
|
2011-04-15 23:51:11 +02:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 09:42:06 +02:00
|
|
|
|
2008-11-24 08:34:46 +01:00
|
|
|
include "llvm/Target/Target.td"
|
2007-06-06 09:42:06 +02:00
|
|
|
|
2014-05-07 12:27:09 +02:00
|
|
|
// The overall idea of the PredicateControl class is to chop the Predicates list
|
|
|
|
// into subsets that are usually overridden independently. This allows
|
|
|
|
// subclasses to partially override the predicates of their superclasses without
|
|
|
|
// having to re-add all the existing predicates.
|
|
|
|
class PredicateControl {
|
|
|
|
// Predicates for the encoding scheme in use such as HasStdEnc
|
|
|
|
list<Predicate> EncodingPredicates = [];
|
2014-05-07 14:48:37 +02:00
|
|
|
// Predicates for the GPR size such as IsGP64bit
|
|
|
|
list<Predicate> GPRPredicates = [];
|
|
|
|
// Predicates for the FGR size and layout such as IsFP64bit
|
|
|
|
list<Predicate> FGRPredicates = [];
|
2014-05-07 15:57:22 +02:00
|
|
|
// Predicates for the instruction group membership such as ISA's and ASE's
|
|
|
|
list<Predicate> InsnPredicates = [];
|
2014-05-07 12:27:09 +02:00
|
|
|
// Predicates for anything else
|
|
|
|
list<Predicate> AdditionalPredicates = [];
|
|
|
|
list<Predicate> Predicates = !listconcat(EncodingPredicates,
|
2014-05-07 14:48:37 +02:00
|
|
|
GPRPredicates,
|
|
|
|
FGRPredicates,
|
2014-05-07 15:57:22 +02:00
|
|
|
InsnPredicates,
|
2014-05-07 12:27:09 +02:00
|
|
|
AdditionalPredicates);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Like Requires<> but for the AdditionalPredicates list
|
|
|
|
class AdditionalRequires<list<Predicate> preds> {
|
|
|
|
list<Predicate> AdditionalPredicates = preds;
|
|
|
|
}
|
|
|
|
|
2011-04-15 23:51:11 +02:00
|
|
|
//===----------------------------------------------------------------------===//
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
|
|
|
// Register File, Calling Conv, Instruction Descriptions
|
2011-04-15 23:51:11 +02:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 09:42:06 +02:00
|
|
|
|
|
|
|
include "MipsRegisterInfo.td"
|
2007-08-18 04:18:07 +02:00
|
|
|
include "MipsSchedule.td"
|
2007-06-06 09:42:06 +02:00
|
|
|
include "MipsInstrInfo.td"
|
2007-08-18 04:18:07 +02:00
|
|
|
include "MipsCallingConv.td"
|
2007-06-06 09:42:06 +02:00
|
|
|
|
2010-04-05 05:10:20 +02:00
|
|
|
def MipsInstrInfo : InstrInfo;
|
2007-08-18 04:18:07 +02:00
|
|
|
|
2011-04-15 23:51:11 +02:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Mips Subtarget features //
|
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 09:42:06 +02:00
|
|
|
|
2014-08-08 17:47:17 +02:00
|
|
|
def FeatureNoABICalls : SubtargetFeature<"noabicalls", "NoABICalls", "true",
|
|
|
|
"Disable SVR4-style position-independent code.">;
|
2008-07-09 07:32:22 +02:00
|
|
|
def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
|
|
|
"General Purpose Registers are 64-bit wide.">;
|
2008-07-09 07:32:22 +02:00
|
|
|
def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
|
2013-10-30 03:29:43 +01:00
|
|
|
"Support 64-bit FP registers.">;
|
2014-07-10 17:36:12 +02:00
|
|
|
def FeatureFPXX : SubtargetFeature<"fpxx", "IsFPXX", "true",
|
|
|
|
"Support for FPXX.">;
|
2014-04-16 17:48:55 +02:00
|
|
|
def FeatureNaN2008 : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
|
|
|
|
"IEEE 754-2008 NaN encoding.">;
|
2008-07-09 07:32:22 +02:00
|
|
|
def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
|
2011-04-15 23:51:11 +02:00
|
|
|
"true", "Only supports single precision float">;
|
2014-07-10 15:38:23 +02:00
|
|
|
def FeatureNoOddSPReg : SubtargetFeature<"nooddspreg", "UseOddSPReg", "false",
|
|
|
|
"Disable odd numbered single-precision "
|
|
|
|
"registers">;
|
2010-11-08 22:42:32 +01:00
|
|
|
def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
|
2008-07-09 07:32:22 +02:00
|
|
|
"true", "Enable vector FPU instructions.">;
|
2014-05-07 18:25:22 +02:00
|
|
|
def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
|
|
|
|
"Mips I ISA Support [highly experimental]">;
|
|
|
|
def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
|
|
|
|
"Mips II ISA Support [highly experimental]",
|
|
|
|
[FeatureMips1]>;
|
2014-05-09 15:02:27 +02:00
|
|
|
def FeatureMips3_32 : SubtargetFeature<"mips3_32", "HasMips3_32", "true",
|
|
|
|
"Subset of MIPS-III that is also in MIPS32 "
|
|
|
|
"[highly experimental]">;
|
2014-05-13 13:45:36 +02:00
|
|
|
def FeatureMips3_32r2 : SubtargetFeature<"mips3_32r2", "HasMips3_32r2", "true",
|
|
|
|
"Subset of MIPS-III that is also in MIPS32r2 "
|
|
|
|
"[highly experimental]">;
|
2014-05-09 15:02:27 +02:00
|
|
|
def FeatureMips3 : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3",
|
|
|
|
"MIPS III ISA Support [highly experimental]",
|
|
|
|
[FeatureMips2, FeatureMips3_32,
|
2014-05-13 13:45:36 +02:00
|
|
|
FeatureMips3_32r2, FeatureGP64Bit,
|
|
|
|
FeatureFP64Bit]>;
|
2014-05-09 16:06:17 +02:00
|
|
|
def FeatureMips4_32 : SubtargetFeature<"mips4_32", "HasMips4_32", "true",
|
|
|
|
"Subset of MIPS-IV that is also in MIPS32 "
|
|
|
|
"[highly experimental]">;
|
2014-05-12 13:56:16 +02:00
|
|
|
def FeatureMips4_32r2 : SubtargetFeature<"mips4_32r2", "HasMips4_32r2", "true",
|
|
|
|
"Subset of MIPS-IV that is also in MIPS32r2 "
|
|
|
|
"[highly experimental]">;
|
2014-05-09 15:02:27 +02:00
|
|
|
def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion",
|
|
|
|
"Mips4", "MIPS IV ISA Support",
|
2014-05-09 16:06:17 +02:00
|
|
|
[FeatureMips3, FeatureMips4_32,
|
2014-05-12 13:56:16 +02:00
|
|
|
FeatureMips4_32r2]>;
|
2014-05-12 14:52:44 +02:00
|
|
|
def FeatureMips5_32r2 : SubtargetFeature<"mips5_32r2", "HasMips5_32r2", "true",
|
|
|
|
"Subset of MIPS-V that is also in MIPS32r2 "
|
|
|
|
"[highly experimental]">;
|
2014-05-09 15:02:27 +02:00
|
|
|
def FeatureMips5 : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5",
|
|
|
|
"MIPS V ISA Support [highly experimental]",
|
2014-05-12 14:52:44 +02:00
|
|
|
[FeatureMips4, FeatureMips5_32r2]>;
|
2011-04-15 23:51:11 +02:00
|
|
|
def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
|
|
|
|
"Mips32 ISA Support",
|
2014-05-09 15:02:27 +02:00
|
|
|
[FeatureMips2, FeatureMips3_32,
|
2014-05-12 14:41:59 +02:00
|
|
|
FeatureMips4_32]>;
|
2010-11-08 22:42:32 +01:00
|
|
|
def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
|
|
|
|
"Mips32r2", "Mips32r2 ISA Support",
|
2014-05-13 13:45:36 +02:00
|
|
|
[FeatureMips3_32r2, FeatureMips4_32r2,
|
|
|
|
FeatureMips5_32r2, FeatureMips32]>;
|
2014-05-09 11:46:21 +02:00
|
|
|
def FeatureMips32r6 : SubtargetFeature<"mips32r6", "MipsArchVersion",
|
|
|
|
"Mips32r6",
|
|
|
|
"Mips32r6 ISA Support [experimental]",
|
|
|
|
[FeatureMips32r2, FeatureFP64Bit,
|
|
|
|
FeatureNaN2008]>;
|
2011-09-20 22:28:08 +02:00
|
|
|
def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion",
|
|
|
|
"Mips64", "Mips64 ISA Support",
|
2014-05-12 13:56:16 +02:00
|
|
|
[FeatureMips5, FeatureMips32]>;
|
2011-09-20 22:28:08 +02:00
|
|
|
def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion",
|
|
|
|
"Mips64r2", "Mips64r2 ISA Support",
|
|
|
|
[FeatureMips64, FeatureMips32r2]>;
|
2014-05-09 11:46:21 +02:00
|
|
|
def FeatureMips64r6 : SubtargetFeature<"mips64r6", "MipsArchVersion",
|
|
|
|
"Mips64r6",
|
|
|
|
"Mips64r6 ISA Support [experimental]",
|
2014-05-12 17:12:45 +02:00
|
|
|
[FeatureMips32r6, FeatureMips64r2,
|
|
|
|
FeatureNaN2008]>;
|
2007-06-06 09:42:06 +02:00
|
|
|
|
2012-05-17 00:19:56 +02:00
|
|
|
def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true",
|
|
|
|
"Mips16 mode">;
|
|
|
|
|
2012-09-22 01:41:49 +02:00
|
|
|
def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
|
|
|
|
def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
|
|
|
|
"Mips DSP-R2 ASE", [FeatureDSP]>;
|
|
|
|
|
2013-08-13 22:54:07 +02:00
|
|
|
def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
|
|
|
|
|
2013-02-05 10:30:03 +01:00
|
|
|
def FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
|
|
|
|
"microMips mode">;
|
|
|
|
|
2014-03-20 12:51:58 +01:00
|
|
|
def FeatureCnMips : SubtargetFeature<"cnmips", "HasCnMips",
|
|
|
|
"true", "Octeon cnMIPS Support",
|
|
|
|
[FeatureMips64r2]>;
|
|
|
|
|
2011-04-15 23:51:11 +02:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 09:42:06 +02:00
|
|
|
// Mips processors supported.
|
2011-04-15 23:51:11 +02:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 09:42:06 +02:00
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
|
|
|
class Proc<string Name, list<SubtargetFeature> Features>
|
|
|
|
: Processor<Name, MipsGenericItineraries, Features>;
|
|
|
|
|
2015-01-26 18:33:46 +01:00
|
|
|
def : Proc<"mips1", [FeatureMips1]>;
|
|
|
|
def : Proc<"mips2", [FeatureMips2]>;
|
|
|
|
def : Proc<"mips32", [FeatureMips32]>;
|
|
|
|
def : Proc<"mips32r2", [FeatureMips32r2]>;
|
|
|
|
def : Proc<"mips32r6", [FeatureMips32r6]>;
|
|
|
|
|
|
|
|
def : Proc<"mips3", [FeatureMips3]>;
|
|
|
|
def : Proc<"mips4", [FeatureMips4]>;
|
|
|
|
def : Proc<"mips5", [FeatureMips5]>;
|
|
|
|
def : Proc<"mips64", [FeatureMips64]>;
|
|
|
|
def : Proc<"mips64r2", [FeatureMips64r2]>;
|
|
|
|
def : Proc<"mips64r6", [FeatureMips64r6]>;
|
|
|
|
def : Proc<"mips16", [FeatureMips16]>;
|
|
|
|
def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>;
|
2010-11-08 22:42:32 +01:00
|
|
|
|
2012-08-17 22:16:42 +02:00
|
|
|
def MipsAsmParser : AsmParser {
|
|
|
|
let ShouldEmitMatchRegisterName = 0;
|
2013-08-01 11:25:27 +02:00
|
|
|
let MnemonicContainsDot = 1;
|
2012-08-17 22:16:42 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
def MipsAsmParserVariant : AsmParserVariant {
|
|
|
|
int Variant = 0;
|
|
|
|
|
|
|
|
// Recognize hard coded registers.
|
|
|
|
string RegisterPrefix = "$";
|
|
|
|
}
|
|
|
|
|
2007-06-06 09:42:06 +02:00
|
|
|
def Mips : Target {
|
|
|
|
let InstructionSet = MipsInstrInfo;
|
2012-08-17 22:16:42 +02:00
|
|
|
let AssemblyParsers = [MipsAsmParser];
|
|
|
|
let AssemblyParserVariants = [MipsAsmParserVariant];
|
2007-06-06 09:42:06 +02:00
|
|
|
}
|