llvm-mirror/test/CodeGen/X86/2008-08-19-SubAndFetch.ll

; RUN: llc < %s -march=x86-64 | FileCheck %s

@var = external global i64		; <i64*> [#uses=1]

define i32 @main() nounwind {
entry:
; CHECK-LABEL: main:
; CHECK: lock
; CHECK: decq
	atomicrmw sub i64* @var, i64 1 monotonic
	unreachable
}
Eliminate more uses of llvm-as and llvm-dis. llvm-svn: 81290 2009-09-09 01:54:48 +02:00			`; RUN: llc < %s -march=x86-64 \| FileCheck %s`
Add support for the __sync_sub_and_fetch atomics and friends for X86. The code was already present, but not hooked up to anything. llvm-svn: 55018 2008-08-20 01:09:18 +02:00
			`@var = external global i64 ; <i64*> [#uses=1]`

			`define i32 @main() nounwind {`
			`entry:`
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name ".ll" \| \ while read NAME; do echo "$NAME" if ! grep -q "^; RUN: llc.debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]@\([A-Za-z0-9_]\)(.$/\1/p" < $NAME \| \ while read FUNC; do sed -i '' "s/;\(.\)\([A-Za-z0-9_-]\):\( \)$FUNC: \$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280 2013-07-14 08:24:09 +02:00			`; CHECK-LABEL: main:`
Optimize some common usage patterns of atomic built-ins __sync_add_and_fetch() and __sync_sub_and_fetch. When the return value is not used (i.e. only care about the value in the memory), x86 does not have to use add to implement these. Instead, it can use add, sub, inc, dec instructions with the "lock" prefix. This is currently implemented using a bit of instruction selection trick. The issue is the target independent pattern produces one output and a chain and we want to map it into one that just output a chain. The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. DAG combiner can then transform the node before it gets to target node selection. Problem #2 is we are adding a whole bunch of x86 atomic instructions when in fact these instructions are identical to the non-lock versions. We need a way to add target specific information to target nodes and have this information carried over to machine instructions. Asm printer (or JIT) can use this information to add the "lock" prefix. llvm-svn: 77582 2009-07-30 10:33:02 +02:00			`; CHECK: lock`
			`; CHECK: decq`
Convert a bunch more tests over to the new atomic instructions. llvm-svn: 140582 2011-09-27 01:15:09 +02:00			`atomicrmw sub i64* @var, i64 1 monotonic`
Add support for the __sync_sub_and_fetch atomics and friends for X86. The code was already present, but not hooked up to anything. llvm-svn: 55018 2008-08-20 01:09:18 +02:00			`unreachable`
			`}`