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llvm-mirror/test/MC/ARM/neon-convert-encoding.s

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Add Neon VCVT instructions for f32 <-> f16 conversions. Clang is now providing intrinsics for these and so we need to support them in the backend. Radar 8068427. llvm-svn: 121902
2010-12-15 23:14:12 +01:00
@ RUN: llvm-mc -mcpu=cortex-a9 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
Covert this test to .s form. llvm-svn: 117684
2010-10-29 21:05:26 +02:00
Use ARM-style comment syntax. llvm-svn: 117941
2010-11-01 19:33:37 +01:00
@ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0x20,0x07,0xfb,0xf3]
Covert this test to .s form. llvm-svn: 117684
2010-10-29 21:05:26 +02:00
vcvt.s32.f32 d16, d16
Use ARM-style comment syntax. llvm-svn: 117941
2010-11-01 19:33:37 +01:00
@ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xa0,0x07,0xfb,0xf3]
Covert this test to .s form. llvm-svn: 117684
2010-10-29 21:05:26 +02:00
vcvt.u32.f32 d16, d16
Use ARM-style comment syntax. llvm-svn: 117941
2010-11-01 19:33:37 +01:00
@ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0x20,0x06,0xfb,0xf3]
Covert this test to .s form. llvm-svn: 117684
2010-10-29 21:05:26 +02:00
vcvt.f32.s32 d16, d16
Use ARM-style comment syntax. llvm-svn: 117941
2010-11-01 19:33:37 +01:00
@ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xa0,0x06,0xfb,0xf3]
Covert this test to .s form. llvm-svn: 117684
2010-10-29 21:05:26 +02:00
vcvt.f32.u32 d16, d16
Use ARM-style comment syntax. llvm-svn: 117941
2010-11-01 19:33:37 +01:00
@ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0x60,0x07,0xfb,0xf3]
Covert this test to .s form. llvm-svn: 117684
2010-10-29 21:05:26 +02:00
vcvt.s32.f32 q8, q8
Use ARM-style comment syntax. llvm-svn: 117941
2010-11-01 19:33:37 +01:00
@ CHECK: vcvt.u32.f32 q8, q8 @ encoding: [0xe0,0x07,0xfb,0xf3]
Covert this test to .s form. llvm-svn: 117684
2010-10-29 21:05:26 +02:00
vcvt.u32.f32 q8, q8
Use ARM-style comment syntax. llvm-svn: 117941
2010-11-01 19:33:37 +01:00
@ CHECK: vcvt.f32.s32 q8, q8 @ encoding: [0x60,0x06,0xfb,0xf3]
Covert this test to .s form. llvm-svn: 117684
2010-10-29 21:05:26 +02:00
vcvt.f32.s32 q8, q8
Use ARM-style comment syntax. llvm-svn: 117941
2010-11-01 19:33:37 +01:00
@ CHECK: vcvt.f32.u32 q8, q8 @ encoding: [0xe0,0x06,0xfb,0xf3]
Covert this test to .s form. llvm-svn: 117684
2010-10-29 21:05:26 +02:00
vcvt.f32.u32 q8, q8
Use ARM-style comment syntax. llvm-svn: 117941
2010-11-01 19:33:37 +01:00
@ CHECK: vcvt.s32.f32 d16, d16, #1 @ encoding: [0x30,0x0f,0xff,0xf2]
Covert this test to .s form. llvm-svn: 117684
2010-10-29 21:05:26 +02:00
vcvt.s32.f32 d16, d16, #1
Fix ARM vcvt encoding when the number of fractional bits is zero. The instruction to convert between floating point and fixed point representations takes an immediate operand for the number of fractional bits of the fixed point value. ARMARM specifies that when that number of bits is zero, the assembler should encode floating point/integer conversion instructions. This patch adds the necessary instruction aliases to achieve this behaviour. llvm-svn: 189009
2013-08-22 15:16:07 +02:00
@ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0x20,0x07,0xfb,0xf3]
vcvt.s32.f32 d16, d16, #0
Use ARM-style comment syntax. llvm-svn: 117941
2010-11-01 19:33:37 +01:00
@ CHECK: vcvt.u32.f32 d16, d16, #1 @ encoding: [0x30,0x0f,0xff,0xf3]
Covert this test to .s form. llvm-svn: 117684
2010-10-29 21:05:26 +02:00
vcvt.u32.f32 d16, d16, #1
Fix ARM vcvt encoding when the number of fractional bits is zero. The instruction to convert between floating point and fixed point representations takes an immediate operand for the number of fractional bits of the fixed point value. ARMARM specifies that when that number of bits is zero, the assembler should encode floating point/integer conversion instructions. This patch adds the necessary instruction aliases to achieve this behaviour. llvm-svn: 189009
2013-08-22 15:16:07 +02:00
@ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xa0,0x07,0xfb,0xf3]
vcvt.u32.f32 d16, d16, #0
Use ARM-style comment syntax. llvm-svn: 117941
2010-11-01 19:33:37 +01:00
@ CHECK: vcvt.f32.s32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xf2]
Covert this test to .s form. llvm-svn: 117684
2010-10-29 21:05:26 +02:00
vcvt.f32.s32 d16, d16, #1
Fix ARM vcvt encoding when the number of fractional bits is zero. The instruction to convert between floating point and fixed point representations takes an immediate operand for the number of fractional bits of the fixed point value. ARMARM specifies that when that number of bits is zero, the assembler should encode floating point/integer conversion instructions. This patch adds the necessary instruction aliases to achieve this behaviour. llvm-svn: 189009
2013-08-22 15:16:07 +02:00
@ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0x20,0x06,0xfb,0xf3]
vcvt.f32.s32 d16, d16, #0
Use ARM-style comment syntax. llvm-svn: 117941
2010-11-01 19:33:37 +01:00
@ CHECK: vcvt.f32.u32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xf3]
Covert this test to .s form. llvm-svn: 117684
2010-10-29 21:05:26 +02:00
vcvt.f32.u32 d16, d16, #1
Fix ARM vcvt encoding when the number of fractional bits is zero. The instruction to convert between floating point and fixed point representations takes an immediate operand for the number of fractional bits of the fixed point value. ARMARM specifies that when that number of bits is zero, the assembler should encode floating point/integer conversion instructions. This patch adds the necessary instruction aliases to achieve this behaviour. llvm-svn: 189009
2013-08-22 15:16:07 +02:00
@ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xa0,0x06,0xfb,0xf3]
vcvt.f32.u32 d16, d16, #0
Use ARM-style comment syntax. llvm-svn: 117941
2010-11-01 19:33:37 +01:00
@ CHECK: vcvt.s32.f32 q8, q8, #1 @ encoding: [0x70,0x0f,0xff,0xf2]
Covert this test to .s form. llvm-svn: 117684
2010-10-29 21:05:26 +02:00
vcvt.s32.f32 q8, q8, #1
Fix ARM vcvt encoding when the number of fractional bits is zero. The instruction to convert between floating point and fixed point representations takes an immediate operand for the number of fractional bits of the fixed point value. ARMARM specifies that when that number of bits is zero, the assembler should encode floating point/integer conversion instructions. This patch adds the necessary instruction aliases to achieve this behaviour. llvm-svn: 189009
2013-08-22 15:16:07 +02:00
@ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0x60,0x07,0xfb,0xf3]
vcvt.s32.f32 q8, q8, #0
Use ARM-style comment syntax. llvm-svn: 117941
2010-11-01 19:33:37 +01:00
@ CHECK: vcvt.u32.f32 q8, q8, #1 @ encoding: [0x70,0x0f,0xff,0xf3]
Covert this test to .s form. llvm-svn: 117684
2010-10-29 21:05:26 +02:00
vcvt.u32.f32 q8, q8, #1
Fix ARM vcvt encoding when the number of fractional bits is zero. The instruction to convert between floating point and fixed point representations takes an immediate operand for the number of fractional bits of the fixed point value. ARMARM specifies that when that number of bits is zero, the assembler should encode floating point/integer conversion instructions. This patch adds the necessary instruction aliases to achieve this behaviour. llvm-svn: 189009
2013-08-22 15:16:07 +02:00
@ CHECK: vcvt.u32.f32 q8, q8 @ encoding: [0xe0,0x07,0xfb,0xf3]
vcvt.u32.f32 q8, q8, #0
Use ARM-style comment syntax. llvm-svn: 117941
2010-11-01 19:33:37 +01:00
@ CHECK: vcvt.f32.s32 q8, q8, #1 @ encoding: [0x70,0x0e,0xff,0xf2]
Covert this test to .s form. llvm-svn: 117684
2010-10-29 21:05:26 +02:00
vcvt.f32.s32 q8, q8, #1
Fix ARM vcvt encoding when the number of fractional bits is zero. The instruction to convert between floating point and fixed point representations takes an immediate operand for the number of fractional bits of the fixed point value. ARMARM specifies that when that number of bits is zero, the assembler should encode floating point/integer conversion instructions. This patch adds the necessary instruction aliases to achieve this behaviour. llvm-svn: 189009
2013-08-22 15:16:07 +02:00
@ CHECK: vcvt.f32.s32 q8, q8 @ encoding: [0x60,0x06,0xfb,0xf3]
vcvt.f32.s32 q8, q8, #0
Use ARM-style comment syntax. llvm-svn: 117941
2010-11-01 19:33:37 +01:00
@ CHECK: vcvt.f32.u32 q8, q8, #1 @ encoding: [0x70,0x0e,0xff,0xf3]
Covert this test to .s form. llvm-svn: 117684
2010-10-29 21:05:26 +02:00
vcvt.f32.u32 q8, q8, #1
Fix ARM vcvt encoding when the number of fractional bits is zero. The instruction to convert between floating point and fixed point representations takes an immediate operand for the number of fractional bits of the fixed point value. ARMARM specifies that when that number of bits is zero, the assembler should encode floating point/integer conversion instructions. This patch adds the necessary instruction aliases to achieve this behaviour. llvm-svn: 189009
2013-08-22 15:16:07 +02:00
@ CHECK: vcvt.f32.u32 q8, q8 @ encoding: [0xe0,0x06,0xfb,0xf3]
vcvt.f32.u32 q8, q8, #0
Add Neon VCVT instructions for f32 <-> f16 conversions. Clang is now providing intrinsics for these and so we need to support them in the backend. Radar 8068427. llvm-svn: 121902
2010-12-15 23:14:12 +01:00
@ CHECK: vcvt.f32.f16 q8, d16 @ encoding: [0x20,0x07,0xf6,0xf3]
vcvt.f32.f16 q8, d16
@ CHECK: vcvt.f16.f32 d16, q8 @ encoding: [0x20,0x06,0xf6,0xf3]
vcvt.f16.f32 d16, q8
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