llvm-mirror/test/CodeGen/X86/pre-split1.ll

; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -regalloc=linearscan -stats |& \
; RUN:   grep {pre-alloc-split} | grep {Number of intervals split} | grep 1
; XFAIL: *

define void @test(double* %P, i32 %cond) nounwind {
entry:
	%0 = load double* %P, align 8		; <double> [#uses=1]
	%1 = fadd double %0, 4.000000e+00		; <double> [#uses=2]
	%2 = icmp eq i32 %cond, 0		; <i1> [#uses=1]
	br i1 %2, label %bb1, label %bb

bb:		; preds = %entry
	%3 = fadd double %1, 4.000000e+00		; <double> [#uses=1]
	br label %bb1

bb1:		; preds = %bb, %entry
	%A.0 = phi double [ %3, %bb ], [ %1, %entry ]		; <double> [#uses=1]
	%4 = fmul double %A.0, 4.000000e+00		; <double> [#uses=1]
	%5 = tail call i32 (...)* @bar() nounwind		; <i32> [#uses=0]
	store double %4, double* %P, align 8
	ret void
}

declare i32 @bar(...)
Fix register-dependent X86 tests. llvm-svn: 128867 2011-04-05 02:32:44 +02:00			`; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -regalloc=linearscan -stats \|& \`
Avoid splitting an interval multiple times; avoid splitting re-materializable val# (for now). llvm-svn: 58068 2008-10-24 04:05:00 +02:00			`; RUN: grep {pre-alloc-split} \| grep {Number of intervals split} \| grep 1`
XFAIL this test. It only worked before because of a bug in the spill point selection code. Not deleting because it should be possible to enhance the selection code to handle this in the future. llvm-svn: 63340 2009-01-29 23:27:56 +01:00			`; XFAIL: *`
Avoid splitting an interval multiple times; avoid splitting re-materializable val# (for now). llvm-svn: 58068 2008-10-24 04:05:00 +02:00
			`define void @test(double* %P, i32 %cond) nounwind {`
			`entry:`
			`%0 = load double* %P, align 8 ; <double> [#uses=1]`
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897 2009-06-05 00:49:04 +02:00			`%1 = fadd double %0, 4.000000e+00 ; <double> [#uses=2]`
Avoid splitting an interval multiple times; avoid splitting re-materializable val# (for now). llvm-svn: 58068 2008-10-24 04:05:00 +02:00			`%2 = icmp eq i32 %cond, 0 ; <i1> [#uses=1]`
			`br i1 %2, label %bb1, label %bb`

			`bb: ; preds = %entry`
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897 2009-06-05 00:49:04 +02:00			`%3 = fadd double %1, 4.000000e+00 ; <double> [#uses=1]`
Avoid splitting an interval multiple times; avoid splitting re-materializable val# (for now). llvm-svn: 58068 2008-10-24 04:05:00 +02:00			`br label %bb1`

			`bb1: ; preds = %bb, %entry`
			`%A.0 = phi double [ %3, %bb ], [ %1, %entry ] ; <double> [#uses=1]`
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897 2009-06-05 00:49:04 +02:00			`%4 = fmul double %A.0, 4.000000e+00 ; <double> [#uses=1]`
Avoid splitting an interval multiple times; avoid splitting re-materializable val# (for now). llvm-svn: 58068 2008-10-24 04:05:00 +02:00			`%5 = tail call i32 (...)* @bar() nounwind ; <i32> [#uses=0]`
			`store double %4, double* %P, align 8`
			`ret void`
			`}`

			`declare i32 @bar(...)`