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llvm-mirror/test/MC/ARM/simple-fp-encoding.s

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Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vadd.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x71,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vadd.f64 d16, d17, d16
Improve handling of #-0 offsets for many more pre-indexed addressing modes. llvm-svn: 138754
2011-08-29 21:36:44 +02:00
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vadd.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x30,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vadd.f32 s0, s1, s0
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vsub.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x71,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vsub.f64 d16, d17, d16
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vsub.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x30,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vsub.f32 s0, s1, s0
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vdiv.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0xc1,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vdiv.f64 d16, d17, d16
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vdiv.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x80,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vdiv.f32 s0, s1, s0
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vmul.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x61,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vmul.f64 d16, d17, d16
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vmul.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x20,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vmul.f32 s0, s1, s0
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vnmul.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x61,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vnmul.f64 d16, d17, d16
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vnmul.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x20,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vnmul.f32 s0, s1, s0
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vcmpe.f64 d17, d16 @ encoding: [0xe0,0x1b,0xf4,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vcmpe.f64 d17, d16
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vcmpe.f32 s1, s0 @ encoding: [0xc0,0x0a,0xf4,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vcmpe.f32 s1, s0
ARM parsing/encoding for VCMP/VCMPE. llvm-svn: 141038
2011-10-04 00:30:24 +02:00
@ CHECK: vcmpe.f64 d16, #0 @ encoding: [0xc0,0x0b,0xf5,0xee]
vcmpe.f64 d16, #0
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
ARM parsing/encoding for VCMP/VCMPE. llvm-svn: 141038
2011-10-04 00:30:24 +02:00
@ CHECK: vcmpe.f32 s0, #0 @ encoding: [0xc0,0x0a,0xb5,0xee]
vcmpe.f32 s0, #0
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vabs.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf0,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vabs.f64 d16, d16
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vabs.f32 s0, s0 @ encoding: [0xc0,0x0a,0xb0,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vabs.f32 s0, s0
Improve handling of #-0 offsets for many more pre-indexed addressing modes. llvm-svn: 138754
2011-08-29 21:36:44 +02:00
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vcvt.f32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xb7,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vcvt.f32.f64 s0, d16
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vcvt.f64.f32 d16, s0 @ encoding: [0xc0,0x0a,0xf7,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vcvt.f64.f32 d16, s0
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vneg.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vneg.f64 d16, d16
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vneg.f32 s0, s0 @ encoding: [0x40,0x0a,0xb1,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vneg.f32 s0, s0
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vsqrt.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf1,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vsqrt.f64 d16, d16
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vsqrt.f32 s0, s0 @ encoding: [0xc0,0x0a,0xb1,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vsqrt.f32 s0, s0
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vcvt.f64.s32 d16, s0 @ encoding: [0xc0,0x0b,0xf8,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vcvt.f64.s32 d16, s0
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vcvt.f32.s32 s0, s0 @ encoding: [0xc0,0x0a,0xb8,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vcvt.f32.s32 s0, s0
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vcvt.f64.u32 d16, s0 @ encoding: [0x40,0x0b,0xf8,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vcvt.f64.u32 d16, s0
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vcvt.f32.u32 s0, s0 @ encoding: [0x40,0x0a,0xb8,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vcvt.f32.u32 s0, s0
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vcvt.s32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbd,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vcvt.s32.f64 s0, d16
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vcvt.s32.f32 s0, s0 @ encoding: [0xc0,0x0a,0xbd,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vcvt.s32.f32 s0, s0
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vcvt.u32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbc,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vcvt.u32.f64 s0, d16
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vcvt.u32.f32 s0, s0 @ encoding: [0xc0,0x0a,0xbc,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vcvt.u32.f32 s0, s0
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vmla.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0x42,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vmla.f64 d16, d18, d17
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vmla.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x41,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vmla.f32 s1, s2, s0
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vmls.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x42,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vmls.f64 d16, d18, d17
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vmls.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x41,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vmls.f32 s1, s2, s0
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vnmla.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x52,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vnmla.f64 d16, d18, d17
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vnmla.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x51,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vnmla.f32 s1, s2, s0
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vnmls.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0x52,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vnmls.f64 d16, d18, d17
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vnmls.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x51,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vnmls.f32 s1, s2, s0
ARM assembly parsing and encoding for VMRS/FMSTAT. llvm-svn: 141025
2011-10-03 23:12:43 +02:00
@ CHECK: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
@ CHECK: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
vmrs apsr_nzcv, fpscr
fmstat
Improve handling of #-0 offsets for many more pre-indexed addressing modes. llvm-svn: 138754
2011-08-29 21:36:44 +02:00
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vnegne.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0x1e]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vnegne.f64 d16, d16
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vmovne s0, r0 @ encoding: [0x10,0x0a,0x00,0x1e]
@ CHECK: vmoveq s0, r1 @ encoding: [0x10,0x1a,0x00,0x0e]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vmovne s0, r0
vmoveq s0, r1
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vmrs r0, fpscr @ encoding: [0x10,0x0a,0xf1,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vmrs r0, fpscr
Create two new generic classes to represent the following VMRS/VMSR variations: vmrs reg, fpexc vmrs reg, fpsid vmsr fpexc, reg vmsr fpsid, reg llvm-svn: 123783
2011-01-18 22:58:20 +01:00
@ CHECK: vmrs r0, fpexc @ encoding: [0x10,0x0a,0xf8,0xee]
vmrs r0, fpexc
@ CHECK: vmrs r0, fpsid @ encoding: [0x10,0x0a,0xf0,0xee]
vmrs r0, fpsid
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vmsr fpscr, r0
Create two new generic classes to represent the following VMRS/VMSR variations: vmrs reg, fpexc vmrs reg, fpsid vmsr fpexc, reg vmsr fpsid, reg llvm-svn: 123783
2011-01-18 22:58:20 +01:00
@ CHECK: vmsr fpexc, r0 @ encoding: [0x10,0x0a,0xe8,0xee]
vmsr fpexc, r0
@ CHECK: vmsr fpsid, r0 @ encoding: [0x10,0x0a,0xe0,0xee]
vmsr fpsid, r0
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
ARM assembly parsing and encoding for VMOV immediate. llvm-svn: 141046
2011-10-04 01:38:36 +02:00
vmov.f64 d16, #3.000000e+00
vmov.f32 s0, #3.000000e+00
vmov.f64 d16, #-3.000000e+00
vmov.f32 s0, #-3.000000e+00
@ CHECK: vmov.f64 d16, #3.000000e+00 @ encoding: [0x08,0x0b,0xf0,0xee]
@ CHECK: vmov.f32 s0, #3.000000e+00 @ encoding: [0x08,0x0a,0xb0,0xee]
@ CHECK: vmov.f64 d16, #-3.000000e+00 @ encoding: [0x08,0x0b,0xf8,0xee]
@ CHECK: vmov.f32 s0, #-3.000000e+00 @ encoding: [0x08,0x0a,0xb8,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vmov s0, r0 @ encoding: [0x10,0x0a,0x00,0xee]
@ CHECK: vmov s1, r1 @ encoding: [0x90,0x1a,0x00,0xee]
@ CHECK: vmov s2, r2 @ encoding: [0x10,0x2a,0x01,0xee]
@ CHECK: vmov s3, r3 @ encoding: [0x90,0x3a,0x01,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vmov s0, r0
vmov s1, r1
vmov s2, r2
vmov s3, r3
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vmov r0, s0 @ encoding: [0x10,0x0a,0x10,0xee]
@ CHECK: vmov r1, s1 @ encoding: [0x90,0x1a,0x10,0xee]
@ CHECK: vmov r2, s2 @ encoding: [0x10,0x2a,0x11,0xee]
@ CHECK: vmov r3, s3 @ encoding: [0x90,0x3a,0x11,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vmov r0, s0
vmov r1, s1
vmov r2, s2
vmov r3, s3
Use ARM-style comments. llvm-svn: 117955
2010-11-01 22:16:39 +01:00
@ CHECK: vmov r0, r1, d16 @ encoding: [0x30,0x0b,0x51,0xec]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. llvm-svn: 117747
2010-10-30 01:50:21 +02:00
vmov r0, r1, d16
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work with immediates up to 16-bits in size. The same logic is applied to other LDR encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in VLDR's case). Removing the "12" allows it to be more generic. llvm-svn: 118094
2010-11-02 23:31:46 +01:00
@ CHECK: vldr.64 d17, [r0] @ encoding: [0x00,0x1b,0xd0,0xed]
vldr.64 d17, [r0]
@ CHECK: vldr.64 d1, [r2, #32] @ encoding: [0x08,0x1b,0x92,0xed]
The MC code couldn't handle ARM LDR instructions with negative offsets: vldr.64 d1, [r0, #-32] The problem was with how the addressing mode 5 encodes the offsets. This change makes sure that the way offsets are handled in addressing mode 5 is consistent throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue" method into an "Imm12" and "addressing mode 5" version. But not to worry! The majority of the duplicated code has been unified. llvm-svn: 118144
2010-11-03 02:49:29 +01:00
@ CHECK: vldr.64 d1, [r2, #-32] @ encoding: [0x08,0x1b,0x12,0xed]
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work with immediates up to 16-bits in size. The same logic is applied to other LDR encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in VLDR's case). Removing the "12" allows it to be more generic. llvm-svn: 118094
2010-11-02 23:31:46 +01:00
vldr.64 d1, [r2, #32]
The MC code couldn't handle ARM LDR instructions with negative offsets: vldr.64 d1, [r0, #-32] The problem was with how the addressing mode 5 encodes the offsets. This change makes sure that the way offsets are handled in addressing mode 5 is consistent throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue" method into an "Imm12" and "addressing mode 5" version. But not to worry! The majority of the duplicated code has been unified. llvm-svn: 118144
2010-11-03 02:49:29 +01:00
vldr.64 d1, [r2, #-32]
Improve handling of #-0 offsets for many more pre-indexed addressing modes. llvm-svn: 138754
2011-08-29 21:36:44 +02:00
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work with immediates up to 16-bits in size. The same logic is applied to other LDR encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in VLDR's case). Removing the "12" allows it to be more generic. llvm-svn: 118094
2010-11-02 23:31:46 +01:00
@ CHECK: vldr.64 d2, [r3] @ encoding: [0x00,0x2b,0x93,0xed]
vldr.64 d2, [r3]
@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed]
@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed]
Improve handling of #-0 offsets for many more pre-indexed addressing modes. llvm-svn: 138754
2011-08-29 21:36:44 +02:00
@ CHECK: vldr.64 d3, [pc, #-0] @ encoding: [0x00,0x3b,0x1f,0xed]
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work with immediates up to 16-bits in size. The same logic is applied to other LDR encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in VLDR's case). Removing the "12" allows it to be more generic. llvm-svn: 118094
2010-11-02 23:31:46 +01:00
vldr.64 d3, [pc]
vldr.64 d3, [pc,#0]
vldr.64 d3, [pc,#-0]
The MC code couldn't handle ARM LDR instructions with negative offsets: vldr.64 d1, [r0, #-32] The problem was with how the addressing mode 5 encodes the offsets. This change makes sure that the way offsets are handled in addressing mode 5 is consistent throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue" method into an "Imm12" and "addressing mode 5" version. But not to worry! The majority of the duplicated code has been unified. llvm-svn: 118144
2010-11-03 02:49:29 +01:00
@ CHECK: vldr.32 s13, [r0] @ encoding: [0x00,0x6a,0xd0,0xed]
vldr.32 s13, [r0]
@ CHECK: vldr.32 s1, [r2, #32] @ encoding: [0x08,0x0a,0xd2,0xed]
@ CHECK: vldr.32 s1, [r2, #-32] @ encoding: [0x08,0x0a,0x52,0xed]
vldr.32 s1, [r2, #32]
vldr.32 s1, [r2, #-32]
Improve handling of #-0 offsets for many more pre-indexed addressing modes. llvm-svn: 138754
2011-08-29 21:36:44 +02:00
The MC code couldn't handle ARM LDR instructions with negative offsets: vldr.64 d1, [r0, #-32] The problem was with how the addressing mode 5 encodes the offsets. This change makes sure that the way offsets are handled in addressing mode 5 is consistent throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue" method into an "Imm12" and "addressing mode 5" version. But not to worry! The majority of the duplicated code has been unified. llvm-svn: 118144
2010-11-03 02:49:29 +01:00
@ CHECK: vldr.32 s2, [r3] @ encoding: [0x00,0x1a,0x93,0xed]
vldr.32 s2, [r3]
@ CHECK: vldr.32 s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed]
@ CHECK: vldr.32 s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed]
Improve handling of #-0 offsets for many more pre-indexed addressing modes. llvm-svn: 138754
2011-08-29 21:36:44 +02:00
@ CHECK: vldr.32 s5, [pc, #-0] @ encoding: [0x00,0x2a,0x5f,0xed]
The MC code couldn't handle ARM LDR instructions with negative offsets: vldr.64 d1, [r0, #-32] The problem was with how the addressing mode 5 encodes the offsets. This change makes sure that the way offsets are handled in addressing mode 5 is consistent throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue" method into an "Imm12" and "addressing mode 5" version. But not to worry! The majority of the duplicated code has been unified. llvm-svn: 118144
2010-11-03 02:49:29 +01:00
vldr.32 s5, [pc]
vldr.32 s5, [pc,#0]
vldr.32 s5, [pc,#-0]
Add encoding for VSTR. llvm-svn: 118220
2010-11-04 01:59:42 +01:00
@ CHECK: vstr.64 d4, [r1] @ encoding: [0x00,0x4b,0x81,0xed]
@ CHECK: vstr.64 d4, [r1, #24] @ encoding: [0x06,0x4b,0x81,0xed]
@ CHECK: vstr.64 d4, [r1, #-24] @ encoding: [0x06,0x4b,0x01,0xed]
vstr.64 d4, [r1]
vstr.64 d4, [r1, #24]
vstr.64 d4, [r1, #-24]
@ CHECK: vstr.32 s4, [r1] @ encoding: [0x00,0x2a,0x81,0xed]
@ CHECK: vstr.32 s4, [r1, #24] @ encoding: [0x06,0x2a,0x81,0xed]
@ CHECK: vstr.32 s4, [r1, #-24] @ encoding: [0x06,0x2a,0x01,0xed]
vstr.32 s4, [r1]
vstr.32 s4, [r1, #24]
vstr.32 s4, [r1, #-24]
Proper encoding for VLDM and VSTM instructions. The register lists for these instructions have to distinguish between lists of single- and double-precision registers in order for the ASM matcher to do a proper job. In all other respects, a list of single- or double-precision registers are the same as a list of GPR registers. llvm-svn: 119460
2010-11-17 05:32:08 +01:00
@ CHECK: vldmia r1, {d2, d3, d4, d5, d6, d7} @ encoding: [0x0c,0x2b,0x91,0xec]
@ CHECK: vldmia r1, {s2, s3, s4, s5, s6, s7} @ encoding: [0x06,0x1a,0x91,0xec]
vldmia r1, {d2,d3-d6,d7}
vldmia r1, {s2,s3-s6,s7}
@ CHECK: vstmia r1, {d2, d3, d4, d5, d6, d7} @ encoding: [0x0c,0x2b,0x81,0xec]
@ CHECK: vstmia r1, {s2, s3, s4, s5, s6, s7} @ encoding: [0x06,0x1a,0x81,0xec]
vstmia r1, {d2,d3-d6,d7}
vstmia r1, {s2,s3-s6,s7}
Add encoding testcases for ARM vcvtr variations llvm-svn: 124289
2011-01-26 14:53:38 +01:00
@ CHECK: vcvtr.s32.f64 s0, d0 @ encoding: [0x40,0x0b,0xbd,0xee]
@ CHECK: vcvtr.s32.f32 s0, s1 @ encoding: [0x60,0x0a,0xbd,0xee]
@ CHECK: vcvtr.u32.f64 s0, d0 @ encoding: [0x40,0x0b,0xbc,0xee]
@ CHECK: vcvtr.u32.f32 s0, s1 @ encoding: [0x60,0x0a,0xbc,0xee]
vcvtr.s32.f64 s0, d0
vcvtr.s32.f32 s0, s1
vcvtr.u32.f64 s0, d0
vcvtr.u32.f32 s0, s1
Add missing encoding information for some of the GPR<->FP register moves. llvm-svn: 138780
2011-08-30 01:15:25 +02:00
@ CHECK: vmovne s25, s26, r2, r5
vmovne s25, s26, r2, r5 @ encoding: [0x39,0x2a,0x45,0x1c]
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