llvm-mirror/test/CodeGen/X86/pr3366.ll

; RUN: llc < %s -march=x86 -disable-cgp-branch-opts | grep movzbl
; PR3366

define void @_ada_c34002a() nounwind {
entry:
  %0 = load i8* null, align 1
  %1 = sdiv i8 90, %0
  %2 = icmp ne i8 %1, 3
  %3 = zext i1 %2 to i8
  %toBool449 = icmp ne i8 %3, 0
  %4 = or i1 false, %toBool449
  %5 = zext i1 %4 to i8
  %toBool450 = icmp ne i8 %5, 0
  br i1 %toBool450, label %bb451, label %bb457

bb451:
  br label %bb457

bb457:
  unreachable
}
As Dan pointed out, movzbl, movsbl, and friends are nicer than their alias (movzx/movsx) because they give more information. Revert that part of the patch. llvm-svn: 129498 2011-04-14 03:46:37 +02:00			`; RUN: llc < %s -march=x86 -disable-cgp-branch-opts \| grep movzbl`
Fix a recent regression. ClrOpcode is not set for i8; for i8, if we want to clear %ah to zero before a division, just use a zero-extending mov to %al. This fixes PR3366. llvm-svn: 62691 2009-01-21 15:50:16 +01:00			`; PR3366`

			`define void @_ada_c34002a() nounwind {`
			`entry:`
			`%0 = load i8* null, align 1`
			`%1 = sdiv i8 90, %0`
			`%2 = icmp ne i8 %1, 3`
			`%3 = zext i1 %2 to i8`
			`%toBool449 = icmp ne i8 %3, 0`
			`%4 = or i1 false, %toBool449`
			`%5 = zext i1 %4 to i8`
			`%toBool450 = icmp ne i8 %5, 0`
			`br i1 %toBool450, label %bb451, label %bb457`

			`bb451:`
			`br label %bb457`

			`bb457:`
			`unreachable`
			`}`