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llvm-mirror/test/CodeGen/AArch64/GlobalISel/select-store.mir

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GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 01:33:31 +02:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
[GlobalISel][AArch64] Split out select tests. NFC. The test has grown enough to be annoying to navigate. While there, Remove unnecessary RUNs, and cleanup a couple comments. llvm-svn: 297856
2017-03-15 17:29:37 +01:00
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
define void @store_s64_gpr(i64* %addr) { ret void }
define void @store_s32_gpr(i32* %addr) { ret void }
define void @store_s16_gpr(i16* %addr) { ret void }
define void @store_s8_gpr(i8* %addr) { ret void }
[GlobalISel][AArch64] Select store of zero to WZR/XZR. These occur very frequently, and are quite trivial to catch. llvm-svn: 298862
2017-03-27 19:31:48 +02:00
define void @store_zero_s64_gpr(i64* %addr) { ret void }
define void @store_zero_s32_gpr(i32* %addr) { ret void }
[GlobalISel][AArch64] Fold FI into LDR/STR ui addressing mode. A majority of loads and stores at O0 access an alloca. It's trivial to fold the G_FRAME_INDEX into the instruction; do it. llvm-svn: 298864
2017-03-27 19:31:56 +02:00
define void @store_fi_s64_gpr() {
%ptr0 = alloca i64
ret void
}
[GlobalISel][AArch64] Fold G_GEP into LDR/STR ui addressing mode. We're not to the point of supporting the load/store patterns yet (because they extensively use PatFrags). But in the meantime, we can implement some of the simplest addressing modes. llvm-svn: 298863
2017-03-27 19:31:52 +02:00
define void @store_gep_128_s64_gpr(i64* %addr) { ret void }
define void @store_gep_512_s32_gpr(i32* %addr) { ret void }
define void @store_gep_64_s16_gpr(i16* %addr) { ret void }
define void @store_gep_1_s8_gpr(i8* %addr) { ret void }
[GlobalISel][AArch64] Split out select tests. NFC. The test has grown enough to be annoying to navigate. While there, Remove unnecessary RUNs, and cleanup a couple comments. llvm-svn: 297856
2017-03-15 17:29:37 +01:00
define void @store_s64_fpr(i64* %addr) { ret void }
define void @store_s32_fpr(i32* %addr) { ret void }
[GlobalISel][AArch64] Fold G_GEP into LDR/STR ui addressing mode. We're not to the point of supporting the load/store patterns yet (because they extensively use PatFrags). But in the meantime, we can implement some of the simplest addressing modes. llvm-svn: 298863
2017-03-27 19:31:52 +02:00
define void @store_gep_8_s64_fpr(i64* %addr) { ret void }
define void @store_gep_8_s32_fpr(i32* %addr) { ret void }
[globalisel][tablegen] Import stores and allow GISel to automatically substitute zero regs like WZR/XZR/$zero. This patch enables the import of stores. Unfortunately, doing so by itself, loses an optimization where storing 0 to memory makes use of WZR/XZR. To mitigate this, this patch also introduces a new feature that allows register operands to nominate a zero register. When this is done, GlobalISel will substitute (G_CONSTANT 0) with the nominated register automatically. This is currently configured to only apply to the stores. Applying it to GPR32/GPR64 register classes in general will be done after review see (https://reviews.llvm.org/D39150). llvm-svn: 316360
2017-10-23 20:19:24 +02:00
define void @store_v2s32(i64 *%addr) { ret void }
[GlobalISel][AArch64] Split out select tests. NFC. The test has grown enough to be annoying to navigate. While there, Remove unnecessary RUNs, and cleanup a couple comments. llvm-svn: 297856
2017-03-15 17:29:37 +01:00
...
---
name: store_s64_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
body: |
bb.0:
liveins: %x0, %x1
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 01:33:31 +02:00
; CHECK-LABEL: name: store_s64_gpr
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-24 20:04:54 +02:00
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 01:33:31 +02:00
; CHECK: STRXui [[COPY1]], [[COPY]], 0 :: (store 8 into %ir.addr)
[GlobalISel][AArch64] Split out select tests. NFC. The test has grown enough to be annoying to navigate. While there, Remove unnecessary RUNs, and cleanup a couple comments. llvm-svn: 297856
2017-03-15 17:29:37 +01:00
%0(p0) = COPY %x0
%1(s64) = COPY %x1
G_STORE %1, %0 :: (store 8 into %ir.addr)
...
---
name: store_s32_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
body: |
bb.0:
liveins: %x0, %w1
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 01:33:31 +02:00
; CHECK-LABEL: name: store_s32_gpr
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-24 20:04:54 +02:00
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 01:33:31 +02:00
; CHECK: STRWui [[COPY1]], [[COPY]], 0 :: (store 4 into %ir.addr)
[GlobalISel][AArch64] Split out select tests. NFC. The test has grown enough to be annoying to navigate. While there, Remove unnecessary RUNs, and cleanup a couple comments. llvm-svn: 297856
2017-03-15 17:29:37 +01:00
%0(p0) = COPY %x0
%1(s32) = COPY %w1
G_STORE %1, %0 :: (store 4 into %ir.addr)
...
---
name: store_s16_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
body: |
bb.0:
liveins: %x0, %w1
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 01:33:31 +02:00
; CHECK-LABEL: name: store_s16_gpr
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-24 20:04:54 +02:00
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
[GISel]: Remove redundant copies at the end of ISel https://reviews.llvm.org/D42402 A lot of these copies are useless (copies b/w VRegs having the same regclass) and should be cleaned up. llvm-svn: 323291
2018-01-24 02:35:26 +01:00
; CHECK: STRHHui [[COPY1]], [[COPY]], 0 :: (store 2 into %ir.addr)
[GlobalISel][AArch64] Split out select tests. NFC. The test has grown enough to be annoying to navigate. While there, Remove unnecessary RUNs, and cleanup a couple comments. llvm-svn: 297856
2017-03-15 17:29:37 +01:00
%0(p0) = COPY %x0
[GISel][AArch64]: Fix illegal Generic copies in tests This is in preparation for a verifier check that makes sure copies are of the same size (when generic virtual registers are involved). llvm-svn: 316387
2017-10-24 00:53:04 +02:00
%2:gpr(s32) = COPY %w1
%1(s16) = G_TRUNC %2
[GlobalISel][AArch64] Split out select tests. NFC. The test has grown enough to be annoying to navigate. While there, Remove unnecessary RUNs, and cleanup a couple comments. llvm-svn: 297856
2017-03-15 17:29:37 +01:00
G_STORE %1, %0 :: (store 2 into %ir.addr)
...
---
name: store_s8_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
body: |
bb.0:
liveins: %x0, %w1
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 01:33:31 +02:00
; CHECK-LABEL: name: store_s8_gpr
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-24 20:04:54 +02:00
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
[GISel]: Remove redundant copies at the end of ISel https://reviews.llvm.org/D42402 A lot of these copies are useless (copies b/w VRegs having the same regclass) and should be cleaned up. llvm-svn: 323291
2018-01-24 02:35:26 +01:00
; CHECK: STRBBui [[COPY1]], [[COPY]], 0 :: (store 1 into %ir.addr)
[GlobalISel][AArch64] Split out select tests. NFC. The test has grown enough to be annoying to navigate. While there, Remove unnecessary RUNs, and cleanup a couple comments. llvm-svn: 297856
2017-03-15 17:29:37 +01:00
%0(p0) = COPY %x0
[GISel][AArch64]: Fix illegal Generic copies in tests This is in preparation for a verifier check that makes sure copies are of the same size (when generic virtual registers are involved). llvm-svn: 316387
2017-10-24 00:53:04 +02:00
%2:gpr(s32) = COPY %w1
%1(s8) = G_TRUNC %2
[GlobalISel][AArch64] Split out select tests. NFC. The test has grown enough to be annoying to navigate. While there, Remove unnecessary RUNs, and cleanup a couple comments. llvm-svn: 297856
2017-03-15 17:29:37 +01:00
G_STORE %1, %0 :: (store 1 into %ir.addr)
...
[GlobalISel][AArch64] Select store of zero to WZR/XZR. These occur very frequently, and are quite trivial to catch. llvm-svn: 298862
2017-03-27 19:31:48 +02:00
---
name: store_zero_s64_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
body: |
bb.0:
liveins: %x0, %x1
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 01:33:31 +02:00
; CHECK-LABEL: name: store_zero_s64_gpr
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-24 20:04:54 +02:00
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 01:33:31 +02:00
; CHECK: STRXui %xzr, [[COPY]], 0 :: (store 8 into %ir.addr)
[GlobalISel][AArch64] Select store of zero to WZR/XZR. These occur very frequently, and are quite trivial to catch. llvm-svn: 298862
2017-03-27 19:31:48 +02:00
%0(p0) = COPY %x0
%1(s64) = G_CONSTANT i64 0
G_STORE %1, %0 :: (store 8 into %ir.addr)
...
---
name: store_zero_s32_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
body: |
bb.0:
liveins: %x0
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 01:33:31 +02:00
; CHECK-LABEL: name: store_zero_s32_gpr
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-24 20:04:54 +02:00
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 01:33:31 +02:00
; CHECK: STRWui %wzr, [[COPY]], 0 :: (store 4 into %ir.addr)
[GlobalISel][AArch64] Select store of zero to WZR/XZR. These occur very frequently, and are quite trivial to catch. llvm-svn: 298862
2017-03-27 19:31:48 +02:00
%0(p0) = COPY %x0
%1(s32) = G_CONSTANT i32 0
G_STORE %1, %0 :: (store 4 into %ir.addr)
...
[GlobalISel][AArch64] Fold FI into LDR/STR ui addressing mode. A majority of loads and stores at O0 access an alloca. It's trivial to fold the G_FRAME_INDEX into the instruction; do it. llvm-svn: 298864
2017-03-27 19:31:56 +02:00
---
name: store_fi_s64_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
stack:
- { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 }
body: |
bb.0:
liveins: %x0
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 01:33:31 +02:00
; CHECK-LABEL: name: store_fi_s64_gpr
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-24 20:04:54 +02:00
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 01:33:31 +02:00
; CHECK: STRXui [[COPY]], %stack.0.ptr0, 0 :: (store 8)
[GlobalISel][AArch64] Fold FI into LDR/STR ui addressing mode. A majority of loads and stores at O0 access an alloca. It's trivial to fold the G_FRAME_INDEX into the instruction; do it. llvm-svn: 298864
2017-03-27 19:31:56 +02:00
%0(p0) = COPY %x0
%1(p0) = G_FRAME_INDEX %stack.0.ptr0
G_STORE %0, %1 :: (store 8)
...
[GlobalISel][AArch64] Fold G_GEP into LDR/STR ui addressing mode. We're not to the point of supporting the load/store patterns yet (because they extensively use PatFrags). But in the meantime, we can implement some of the simplest addressing modes. llvm-svn: 298863
2017-03-27 19:31:52 +02:00
---
name: store_gep_128_s64_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
- { id: 3, class: gpr }
body: |
bb.0:
liveins: %x0, %x1
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 01:33:31 +02:00
; CHECK-LABEL: name: store_gep_128_s64_gpr
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-24 20:04:54 +02:00
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 01:33:31 +02:00
; CHECK: STRXui [[COPY1]], [[COPY]], 16 :: (store 8 into %ir.addr)
[GlobalISel][AArch64] Fold G_GEP into LDR/STR ui addressing mode. We're not to the point of supporting the load/store patterns yet (because they extensively use PatFrags). But in the meantime, we can implement some of the simplest addressing modes. llvm-svn: 298863
2017-03-27 19:31:52 +02:00
%0(p0) = COPY %x0
%1(s64) = COPY %x1
%2(s64) = G_CONSTANT i64 128
%3(p0) = G_GEP %0, %2
G_STORE %1, %3 :: (store 8 into %ir.addr)
...
---
name: store_gep_512_s32_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
- { id: 3, class: gpr }
body: |
bb.0:
liveins: %x0, %w1
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 01:33:31 +02:00
; CHECK-LABEL: name: store_gep_512_s32_gpr
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-24 20:04:54 +02:00
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 01:33:31 +02:00
; CHECK: STRWui [[COPY1]], [[COPY]], 128 :: (store 4 into %ir.addr)
[GlobalISel][AArch64] Fold G_GEP into LDR/STR ui addressing mode. We're not to the point of supporting the load/store patterns yet (because they extensively use PatFrags). But in the meantime, we can implement some of the simplest addressing modes. llvm-svn: 298863
2017-03-27 19:31:52 +02:00
%0(p0) = COPY %x0
%1(s32) = COPY %w1
%2(s64) = G_CONSTANT i64 512
%3(p0) = G_GEP %0, %2
G_STORE %1, %3 :: (store 4 into %ir.addr)
...
---
name: store_gep_64_s16_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
- { id: 3, class: gpr }
body: |
bb.0:
liveins: %x0, %w1
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 01:33:31 +02:00
; CHECK-LABEL: name: store_gep_64_s16_gpr
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-24 20:04:54 +02:00
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
[GISel]: Remove redundant copies at the end of ISel https://reviews.llvm.org/D42402 A lot of these copies are useless (copies b/w VRegs having the same regclass) and should be cleaned up. llvm-svn: 323291
2018-01-24 02:35:26 +01:00
; CHECK: STRHHui [[COPY1]], [[COPY]], 32 :: (store 2 into %ir.addr)
[GlobalISel][AArch64] Fold G_GEP into LDR/STR ui addressing mode. We're not to the point of supporting the load/store patterns yet (because they extensively use PatFrags). But in the meantime, we can implement some of the simplest addressing modes. llvm-svn: 298863
2017-03-27 19:31:52 +02:00
%0(p0) = COPY %x0
[GISel][AArch64]: Fix illegal Generic copies in tests This is in preparation for a verifier check that makes sure copies are of the same size (when generic virtual registers are involved). llvm-svn: 316387
2017-10-24 00:53:04 +02:00
%4:gpr(s32) = COPY %w1
%1(s16) = G_TRUNC %4
[GlobalISel][AArch64] Fold G_GEP into LDR/STR ui addressing mode. We're not to the point of supporting the load/store patterns yet (because they extensively use PatFrags). But in the meantime, we can implement some of the simplest addressing modes. llvm-svn: 298863
2017-03-27 19:31:52 +02:00
%2(s64) = G_CONSTANT i64 64
%3(p0) = G_GEP %0, %2
G_STORE %1, %3 :: (store 2 into %ir.addr)
...
---
name: store_gep_1_s8_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
- { id: 3, class: gpr }
body: |
bb.0:
liveins: %x0, %w1
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 01:33:31 +02:00
; CHECK-LABEL: name: store_gep_1_s8_gpr
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-24 20:04:54 +02:00
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
[GISel]: Remove redundant copies at the end of ISel https://reviews.llvm.org/D42402 A lot of these copies are useless (copies b/w VRegs having the same regclass) and should be cleaned up. llvm-svn: 323291
2018-01-24 02:35:26 +01:00
; CHECK: STRBBui [[COPY1]], [[COPY]], 1 :: (store 1 into %ir.addr)
[GlobalISel][AArch64] Fold G_GEP into LDR/STR ui addressing mode. We're not to the point of supporting the load/store patterns yet (because they extensively use PatFrags). But in the meantime, we can implement some of the simplest addressing modes. llvm-svn: 298863
2017-03-27 19:31:52 +02:00
%0(p0) = COPY %x0
[GISel][AArch64]: Fix illegal Generic copies in tests This is in preparation for a verifier check that makes sure copies are of the same size (when generic virtual registers are involved). llvm-svn: 316387
2017-10-24 00:53:04 +02:00
%4:gpr(s32) = COPY %w1
%1(s8) = G_TRUNC %4
[GlobalISel][AArch64] Fold G_GEP into LDR/STR ui addressing mode. We're not to the point of supporting the load/store patterns yet (because they extensively use PatFrags). But in the meantime, we can implement some of the simplest addressing modes. llvm-svn: 298863
2017-03-27 19:31:52 +02:00
%2(s64) = G_CONSTANT i64 1
%3(p0) = G_GEP %0, %2
G_STORE %1, %3 :: (store 1 into %ir.addr)
...
[GlobalISel][AArch64] Split out select tests. NFC. The test has grown enough to be annoying to navigate. While there, Remove unnecessary RUNs, and cleanup a couple comments. llvm-svn: 297856
2017-03-15 17:29:37 +01:00
---
name: store_s64_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
body: |
bb.0:
liveins: %x0, %d1
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 01:33:31 +02:00
; CHECK-LABEL: name: store_s64_fpr
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-24 20:04:54 +02:00
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 01:33:31 +02:00
; CHECK: STRDui [[COPY1]], [[COPY]], 0 :: (store 8 into %ir.addr)
[GlobalISel][AArch64] Split out select tests. NFC. The test has grown enough to be annoying to navigate. While there, Remove unnecessary RUNs, and cleanup a couple comments. llvm-svn: 297856
2017-03-15 17:29:37 +01:00
%0(p0) = COPY %x0
%1(s64) = COPY %d1
G_STORE %1, %0 :: (store 8 into %ir.addr)
...
---
name: store_s32_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
body: |
bb.0:
liveins: %x0, %s1
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 01:33:31 +02:00
; CHECK-LABEL: name: store_s32_fpr
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-24 20:04:54 +02:00
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %s1
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 01:33:31 +02:00
; CHECK: STRSui [[COPY1]], [[COPY]], 0 :: (store 4 into %ir.addr)
[GlobalISel][AArch64] Split out select tests. NFC. The test has grown enough to be annoying to navigate. While there, Remove unnecessary RUNs, and cleanup a couple comments. llvm-svn: 297856
2017-03-15 17:29:37 +01:00
%0(p0) = COPY %x0
%1(s32) = COPY %s1
G_STORE %1, %0 :: (store 4 into %ir.addr)
...
[GlobalISel][AArch64] Fold G_GEP into LDR/STR ui addressing mode. We're not to the point of supporting the load/store patterns yet (because they extensively use PatFrags). But in the meantime, we can implement some of the simplest addressing modes. llvm-svn: 298863
2017-03-27 19:31:52 +02:00
---
name: store_gep_8_s64_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
- { id: 2, class: gpr }
- { id: 3, class: gpr }
body: |
bb.0:
liveins: %x0, %d1
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 01:33:31 +02:00
; CHECK-LABEL: name: store_gep_8_s64_fpr
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-24 20:04:54 +02:00
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 01:33:31 +02:00
; CHECK: STRDui [[COPY1]], [[COPY]], 1 :: (store 8 into %ir.addr)
[GlobalISel][AArch64] Fold G_GEP into LDR/STR ui addressing mode. We're not to the point of supporting the load/store patterns yet (because they extensively use PatFrags). But in the meantime, we can implement some of the simplest addressing modes. llvm-svn: 298863
2017-03-27 19:31:52 +02:00
%0(p0) = COPY %x0
%1(s64) = COPY %d1
%2(s64) = G_CONSTANT i64 8
%3(p0) = G_GEP %0, %2
G_STORE %1, %3 :: (store 8 into %ir.addr)
...
---
name: store_gep_8_s32_fpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
- { id: 2, class: gpr }
- { id: 3, class: gpr }
body: |
bb.0:
liveins: %x0, %s1
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 01:33:31 +02:00
; CHECK-LABEL: name: store_gep_8_s32_fpr
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-24 20:04:54 +02:00
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %s1
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 01:33:31 +02:00
; CHECK: STRSui [[COPY1]], [[COPY]], 2 :: (store 4 into %ir.addr)
[GlobalISel][AArch64] Fold G_GEP into LDR/STR ui addressing mode. We're not to the point of supporting the load/store patterns yet (because they extensively use PatFrags). But in the meantime, we can implement some of the simplest addressing modes. llvm-svn: 298863
2017-03-27 19:31:52 +02:00
%0(p0) = COPY %x0
%1(s32) = COPY %s1
%2(s64) = G_CONSTANT i64 8
%3(p0) = G_GEP %0, %2
G_STORE %1, %3 :: (store 4 into %ir.addr)
...
[globalisel][tablegen] Import stores and allow GISel to automatically substitute zero regs like WZR/XZR/$zero. This patch enables the import of stores. Unfortunately, doing so by itself, loses an optimization where storing 0 to memory makes use of WZR/XZR. To mitigate this, this patch also introduces a new feature that allows register operands to nominate a zero register. When this is done, GlobalISel will substitute (G_CONSTANT 0) with the nominated register automatically. This is currently configured to only apply to the stores. Applying it to GPR32/GPR64 register classes in general will be done after review see (https://reviews.llvm.org/D39150). llvm-svn: 316360
2017-10-23 20:19:24 +02:00
---
name: store_v2s32
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
body: |
bb.0:
liveins: %x0, %d1
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-24 20:04:54 +02:00
; CHECK-LABEL: name: store_v2s32
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
; CHECK: STRDui [[COPY1]], [[COPY]], 0 :: (store 8 into %ir.addr)
[globalisel][tablegen] Import stores and allow GISel to automatically substitute zero regs like WZR/XZR/$zero. This patch enables the import of stores. Unfortunately, doing so by itself, loses an optimization where storing 0 to memory makes use of WZR/XZR. To mitigate this, this patch also introduces a new feature that allows register operands to nominate a zero register. When this is done, GlobalISel will substitute (G_CONSTANT 0) with the nominated register automatically. This is currently configured to only apply to the stores. Applying it to GPR32/GPR64 register classes in general will be done after review see (https://reviews.llvm.org/D39150). llvm-svn: 316360
2017-10-23 20:19:24 +02:00
%0(p0) = COPY %x0
%1(<2 x s32>) = COPY %d1
G_STORE %1, %0 :: (store 8 into %ir.addr)
...
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