llvm-mirror/test/CodeGen/Mips/inlineasm64.ll

; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck %s

@gl2 = external global i64
@gl1 = external global i64
@gl0 = external global i64

define void @foo1() nounwind {
entry:
; CHECK: foo1
; CHECK: daddu
  %0 = load i64, i64* @gl1, align 8
  %1 = load i64, i64* @gl0, align 8
  %2 = tail call i64 asm "daddu $0, $1, $2", "=r,r,r"(i64 %0, i64 %1) nounwind
  store i64 %2, i64* @gl2, align 8
  ret void
}
Replace obsolete -mattr=n64 command line option with -target-abi=n64. No functional changes. llvm-svn: 230628 2015-02-26 13:29:48 +01:00			`; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 < %s \| FileCheck %s`
Have getRegForInlineAsmConstraint return the correct register class when target is Mips64. llvm-svn: 147516 2012-01-04 03:45:01 +01:00
			`@gl2 = external global i64`
			`@gl1 = external global i64`
			`@gl0 = external global i64`

			`define void @foo1() nounwind {`
			`entry:`
			`; CHECK: foo1`
			`; CHECK: daddu`
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=\|:\|^)\sload (?:atomic )?(?:volatile )?(.?))(\| addrspace\(\d+\) )\($\| (?:%\|@\|null\|undef\|blockaddress\|getelementptr\|addrspacecast\|bitcast\|inttoptr\|\[\[[a-zA-Z]\|\{\{).$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794 2015-02-27 22:17:42 +01:00			`%0 = load i64, i64* @gl1, align 8`
			`%1 = load i64, i64* @gl0, align 8`
Have getRegForInlineAsmConstraint return the correct register class when target is Mips64. llvm-svn: 147516 2012-01-04 03:45:01 +01:00			`%2 = tail call i64 asm "daddu $0, $1, $2", "=r,r,r"(i64 %0, i64 %1) nounwind`
			`store i64 %2, i64* @gl2, align 8`
			`ret void`
			`}`