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llvm-mirror/test/CodeGen/Thumb2/thumb2-uxt_rot.ll

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ARM: yet another round of ARM test clean ups llvm-svn: 205586
2014-04-04 01:47:24 +02:00
; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s --check-prefix=A8
; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s --check-prefix=M3
If triple is armv7 / thumbv7 and a CPU is specified, do not automatically assume the feature set of v7a. This comes about if the user specifies something like -arch armv7 -mcpu=cortex-m3. We shouldn't be generating instructions such as uxtab in this case. rdar://11318438 llvm-svn: 155601
2012-04-26 03:13:36 +02:00
; rdar://11318438
Add thumb2 sign / zero extend with rotate instructions. llvm-svn: 74755
2009-07-03 03:43:10 +02:00
manually upgrade a bunch of tests to modern syntax, and remove some that are either unreduced or only test old syntax. llvm-svn: 133228
2011-06-17 05:14:27 +02:00
define zeroext i8 @test1(i32 %A.u) {
Fix test case label check Several (but not all) of the labels that are checked for in this test case are checked as strings instead of labels. This can cause an apparent test case failure if they are tested in an appropriately named directory. For example, one of them that fails: define zeroext i32 @test2(i32 %A.u, i32 %B.u) { ; A8: test2 ; A8: uxtab r0, r0, r1 Output that causes it to fail: . . . .file "/home/seurer/llvm/llvm-test2/test/CodeGen/Thumb2/thumb2-uxt_rot.ll" . . . .globl test2 .align 1 .type test2,%function .code 16 @ @test2 .thumb_func test2: .fnstart The "A8: test2" matches on the directory name instead of the label. llvm-svn: 253702
2015-11-20 21:24:49 +01:00
; A8-LABEL: test1:
If triple is armv7 / thumbv7 and a CPU is specified, do not automatically assume the feature set of v7a. This comes about if the user specifies something like -arch armv7 -mcpu=cortex-m3. We shouldn't be generating instructions such as uxtab in this case. rdar://11318438 llvm-svn: 155601
2012-04-26 03:13:36 +02:00
; A8: uxtb r0, r0
Add thumb2 sign / zero extend with rotate instructions. llvm-svn: 74755
2009-07-03 03:43:10 +02:00
%B.u = trunc i32 %A.u to i8
ret i8 %B.u
}
manually upgrade a bunch of tests to modern syntax, and remove some that are either unreduced or only test old syntax. llvm-svn: 133228
2011-06-17 05:14:27 +02:00
define zeroext i32 @test2(i32 %A.u, i32 %B.u) {
Fix test case label check Several (but not all) of the labels that are checked for in this test case are checked as strings instead of labels. This can cause an apparent test case failure if they are tested in an appropriately named directory. For example, one of them that fails: define zeroext i32 @test2(i32 %A.u, i32 %B.u) { ; A8: test2 ; A8: uxtab r0, r0, r1 Output that causes it to fail: . . . .file "/home/seurer/llvm/llvm-test2/test/CodeGen/Thumb2/thumb2-uxt_rot.ll" . . . .globl test2 .align 1 .type test2,%function .code 16 @ @test2 .thumb_func test2: .fnstart The "A8: test2" matches on the directory name instead of the label. llvm-svn: 253702
2015-11-20 21:24:49 +01:00
; A8-LABEL: test2:
If triple is armv7 / thumbv7 and a CPU is specified, do not automatically assume the feature set of v7a. This comes about if the user specifies something like -arch armv7 -mcpu=cortex-m3. We shouldn't be generating instructions such as uxtab in this case. rdar://11318438 llvm-svn: 155601
2012-04-26 03:13:36 +02:00
; A8: uxtab r0, r0, r1
Fix test case label check Several (but not all) of the labels that are checked for in this test case are checked as strings instead of labels. This can cause an apparent test case failure if they are tested in an appropriately named directory. For example, one of them that fails: define zeroext i32 @test2(i32 %A.u, i32 %B.u) { ; A8: test2 ; A8: uxtab r0, r0, r1 Output that causes it to fail: . . . .file "/home/seurer/llvm/llvm-test2/test/CodeGen/Thumb2/thumb2-uxt_rot.ll" . . . .globl test2 .align 1 .type test2,%function .code 16 @ @test2 .thumb_func test2: .fnstart The "A8: test2" matches on the directory name instead of the label. llvm-svn: 253702
2015-11-20 21:24:49 +01:00
; M3-LABEL: test2:
If triple is armv7 / thumbv7 and a CPU is specified, do not automatically assume the feature set of v7a. This comes about if the user specifies something like -arch armv7 -mcpu=cortex-m3. We shouldn't be generating instructions such as uxtab in this case. rdar://11318438 llvm-svn: 155601
2012-04-26 03:13:36 +02:00
; M3: uxtb r1, r1
; M3-NOT: uxtab
; M3: add r0, r1
Add thumb2 sign / zero extend with rotate instructions. llvm-svn: 74755
2009-07-03 03:43:10 +02:00
%C.u = trunc i32 %B.u to i8
%D.u = zext i8 %C.u to i32
%E.u = add i32 %A.u, %D.u
ret i32 %E.u
}
manually upgrade a bunch of tests to modern syntax, and remove some that are either unreduced or only test old syntax. llvm-svn: 133228
2011-06-17 05:14:27 +02:00
define zeroext i32 @test3(i32 %A.u) {
Fix test case label check Several (but not all) of the labels that are checked for in this test case are checked as strings instead of labels. This can cause an apparent test case failure if they are tested in an appropriately named directory. For example, one of them that fails: define zeroext i32 @test2(i32 %A.u, i32 %B.u) { ; A8: test2 ; A8: uxtab r0, r0, r1 Output that causes it to fail: . . . .file "/home/seurer/llvm/llvm-test2/test/CodeGen/Thumb2/thumb2-uxt_rot.ll" . . . .globl test2 .align 1 .type test2,%function .code 16 @ @test2 .thumb_func test2: .fnstart The "A8: test2" matches on the directory name instead of the label. llvm-svn: 253702
2015-11-20 21:24:49 +01:00
; A8-LABEL: test3:
[SDAG] Make the DAGCombine worklist not grow endlessly due to duplicate insertions. The old behavior could cause arbitrarily bad memory usage in the DAG combiner if there was heavy traffic of adding nodes already on the worklist to it. This commit switches the DAG combine worklist to work the same way as the instcombine worklist where we null-out removed entries and only add new entries to the worklist. My measurements of codegen time shows slight improvement. The memory utilization is unsurprisingly dominated by other factors (the IR and DAG itself I suspect). This change results in subtle, frustrating churn in the particular order in which DAG combines are applied which causes a number of minor regressions where we fail to match a pattern previously matched by accident. AFAICT, all of these should be using AddToWorklist to directly or should be written in a less brittle way. None of the changes seem drastically bad, and a few of the changes seem distinctly better. A major change required to make this work is to significantly harden the way in which the DAG combiner handle nodes which become dead (zero-uses). Previously, we relied on the ability to "priority-bump" them on the combine worklist to achieve recursive deletion of these nodes and ensure that the frontier of remaining live nodes all were added to the worklist. Instead, I've introduced a routine to just implement that precise logic with no indirection. It is a significantly simpler operation than that of the combiner worklist proper. I suspect this will also fix some other problems with the combiner. I think the x86 changes are really minor and uninteresting, but the avx512 change at least is hiding a "regression" (despite the test case being just noise, not testing some performance invariant) that might be looked into. Not sure if any of the others impact specific "important" code paths, but they didn't look terribly interesting to me, or the changes were really minor. The consensus in review is to fix any regressions that show up after the fact here. Thanks to the other reviewers for checking the output on other architectures. There is a specific regression on ARM that Tim already has a fix prepped to commit. Differential Revision: http://reviews.llvm.org/D4616 llvm-svn: 213727
2014-07-23 09:08:53 +02:00
; A8: ubfx r0, r0, #8, #16
Add thumb2 sign / zero extend with rotate instructions. llvm-svn: 74755
2009-07-03 03:43:10 +02:00
%B.u = lshr i32 %A.u, 8
%C.u = shl i32 %A.u, 24
%D.u = or i32 %B.u, %C.u
%E.u = trunc i32 %D.u to i16
%F.u = zext i16 %E.u to i32
ret i32 %F.u
}
ARM: add patterns for [su]xta[bh] from just a shift. Although the final shifter operand is a rotate, this actually only matters for the half-word extends when the amount == 24. Otherwise folding a shift in is just as good. llvm-svn: 213753
2014-07-23 15:59:07 +02:00
define i32 @test4(i32 %A, i32 %X) {
; A8-LABEL: test4:
; A8: uxtab r0, r0, r1, ror #16
%X.hi = lshr i32 %X, 16
%X.trunc = trunc i32 %X.hi to i8
%addend = zext i8 %X.trunc to i32
%sum = add i32 %A, %addend
ret i32 %sum
}
define i32 @test5(i32 %A, i32 %X) {
; A8-LABEL: test5:
; A8: uxtah r0, r0, r1, ror #8
%X.hi = lshr i32 %X, 8
%X.trunc = trunc i32 %X.hi to i16
%addend = zext i16 %X.trunc to i32
%sum = add i32 %A, %addend
ret i32 %sum
}
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