llvm-mirror/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

--- |

  define i8 @zext_i1_to_i8(i1 %val) {
    %res = zext i1 %val to i8
    ret i8 %res
  }

  define i16 @zext_i1_to_i16(i1 %val) {
    %res = zext i1 %val to i16
    ret i16 %res
  }

  define i32 @zext_i1_to_i32(i1 %val) {
    %res = zext i1 %val to i32
    ret i32 %res
  }

  define i64 @zext_i1_to_i64(i1 %val) {
    %res = zext i1 %val to i64
    ret i64 %res
  }

  define i16 @zext_i8_to_i16(i8 %val) {
    %res = zext i8 %val to i16
    ret i16 %res
  }

  define i32 @zext_i8_to_i32(i8 %val) {
    %res = zext i8 %val to i32
    ret i32 %res
  }

  define i64 @zext_i8_to_i64(i8 %val) {
    %res = zext i8 %val to i64
    ret i64 %res
  }

  define i32 @zext_i16_to_i32(i16 %val) {
    %res = zext i16 %val to i32
    ret i32 %res
  }

  define i64 @zext_i16_to_i64(i16 %val) {
    %res = zext i16 %val to i64
    ret i64 %res
  }

  define i64 @zext_i32_to_i64(i32 %val) {
    %res = zext i32 %val to i64
    ret i64 %res
  }

...
---
name:            zext_i1_to_i8
alignment:       16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }
  - { id: 3, class: gpr }
  - { id: 4, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: zext_i1_to_i8
    ; CHECK: liveins: $edi
    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
    ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
    ; CHECK: [[AND8ri:%[0-9]+]]:gr8 = AND8ri [[COPY1]], 1, implicit-def $eflags
    ; CHECK: $al = COPY [[AND8ri]]
    ; CHECK: RET 0, implicit $al
    %1:gpr(s32) = COPY $edi
    %3:gpr(s8) = G_CONSTANT i8 1
    %4:gpr(s8) = G_TRUNC %1(s32)
    %2:gpr(s8) = G_AND %4, %3
    $al = COPY %2(s8)
    RET 0, implicit $al

...
---
name:            zext_i1_to_i16
alignment:       16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }
  - { id: 3, class: gpr }
  - { id: 4, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: zext_i1_to_i16
    ; CHECK: liveins: $edi
    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
    ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
    ; CHECK: [[AND16ri8_:%[0-9]+]]:gr16 = AND16ri8 [[COPY1]], 1, implicit-def $eflags
    ; CHECK: $ax = COPY [[AND16ri8_]]
    ; CHECK: RET 0, implicit $ax
    %1:gpr(s32) = COPY $edi
    %3:gpr(s16) = G_CONSTANT i16 1
    %4:gpr(s16) = G_TRUNC %1(s32)
    %2:gpr(s16) = G_AND %4, %3
    $ax = COPY %2(s16)
    RET 0, implicit $ax

...
---
name:            zext_i1_to_i32
alignment:       16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }
  - { id: 3, class: gpr }
  - { id: 4, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: zext_i1_to_i32
    ; CHECK: liveins: $edi
    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[COPY]], 1, implicit-def $eflags
    ; CHECK: $eax = COPY [[AND32ri8_]]
    ; CHECK: RET 0, implicit $eax
    %1:gpr(s32) = COPY $edi
    %3:gpr(s32) = G_CONSTANT i32 1
    %4:gpr(s32) = COPY %1(s32)
    %2:gpr(s32) = G_AND %4, %3
    $eax = COPY %2(s32)
    RET 0, implicit $eax

...
---
name:            zext_i1_to_i64
alignment:       16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }
  - { id: 3, class: gpr }
  - { id: 4, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: zext_i1_to_i64
    ; CHECK: liveins: $edi
    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
    ; CHECK: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit
    ; CHECK: [[AND64ri8_:%[0-9]+]]:gr64 = AND64ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
    ; CHECK: $rax = COPY [[AND64ri8_]]
    ; CHECK: RET 0, implicit $rax
    %1:gpr(s32) = COPY $edi
    %3:gpr(s64) = G_CONSTANT i64 1
    %4:gpr(s64) = G_ANYEXT %1(s32)
    %2:gpr(s64) = G_AND %4, %3
    $rax = COPY %2(s64)
    RET 0, implicit $rax

...
---
name:            zext_i8_to_i16
alignment:       16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }
  - { id: 3, class: gpr }
  - { id: 4, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: zext_i8_to_i16
    ; CHECK: liveins: $edi
    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
    ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
    ; CHECK: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY2]]
    ; CHECK: [[COPY3:%[0-9]+]]:gr16 = COPY [[MOVZX32rr8_]].sub_16bit
    ; CHECK: $ax = COPY [[COPY3]]
    ; CHECK: RET 0, implicit $ax
    %1:gpr(s32) = COPY $edi
    %3:gpr(s16) = G_CONSTANT i16 255
    %4:gpr(s16) = G_TRUNC %1(s32)
    %2:gpr(s16) = G_AND %4, %3
    $ax = COPY %2(s16)
    RET 0, implicit $ax

...
---
name:            zext_i8_to_i32
alignment:       16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }
  - { id: 3, class: gpr }
  - { id: 4, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: zext_i8_to_i32
    ; CHECK: liveins: $edi
    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
    ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]]
    ; CHECK: $eax = COPY [[MOVZX32rr8_]]
    ; CHECK: RET 0, implicit $eax
    %1:gpr(s32) = COPY $edi
    %3:gpr(s32) = G_CONSTANT i32 255
    %4:gpr(s32) = COPY %1(s32)
    %2:gpr(s32) = G_AND %4, %3
    $eax = COPY %2(s32)
    RET 0, implicit $eax

...
---
name:            zext_i8_to_i64
alignment:       16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }
  - { id: 3, class: gpr }
  - { id: 4, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: zext_i8_to_i64
    ; CHECK: liveins: $edi
    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
    ; CHECK: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit
    ; CHECK: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 255, implicit-def $eflags
    ; CHECK: $rax = COPY [[AND64ri32_]]
    ; CHECK: RET 0, implicit $rax
    %1:gpr(s32) = COPY $edi
    %3:gpr(s64) = G_CONSTANT i64 255
    %4:gpr(s64) = G_ANYEXT %1(s32)
    %2:gpr(s64) = G_AND %4, %3
    $rax = COPY %2(s64)
    RET 0, implicit $rax

...
---
name:            zext_i16_to_i32
alignment:       16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }
  - { id: 3, class: gpr }
  - { id: 4, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: zext_i16_to_i32
    ; CHECK: liveins: $edi
    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
    ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
    ; CHECK: [[MOVZX32rr16_:%[0-9]+]]:gr32 = MOVZX32rr16 [[COPY1]]
    ; CHECK: $eax = COPY [[MOVZX32rr16_]]
    ; CHECK: RET 0, implicit $eax
    %1:gpr(s32) = COPY $edi
    %3:gpr(s32) = G_CONSTANT i32 65535
    %4:gpr(s32) = COPY %1(s32)
    %2:gpr(s32) = G_AND %4, %3
    $eax = COPY %2(s32)
    RET 0, implicit $eax

...
---
name:            zext_i16_to_i64
alignment:       16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }
  - { id: 3, class: gpr }
  - { id: 4, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: zext_i16_to_i64
    ; CHECK: liveins: $edi
    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
    ; CHECK: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit
    ; CHECK: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 65535, implicit-def $eflags
    ; CHECK: $rax = COPY [[AND64ri32_]]
    ; CHECK: RET 0, implicit $rax
    %1:gpr(s32) = COPY $edi
    %3:gpr(s64) = G_CONSTANT i64 65535
    %4:gpr(s64) = G_ANYEXT %1(s32)
    %2:gpr(s64) = G_AND %4, %3
    $rax = COPY %2(s64)
    RET 0, implicit $rax

...
---
name:            zext_i32_to_i64
alignment:       16
legalized:       true
regBankSelected: true
tracksRegLiveness: true
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; CHECK-LABEL: name: zext_i32_to_i64
    ; CHECK: liveins: $edi
    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
    ; CHECK: [[MOV32rr:%[0-9]+]]:gr32 = MOV32rr [[COPY]]
    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[MOV32rr]], %subreg.sub_32bit
    ; CHECK: $rax = COPY [[SUBREG_TO_REG]]
    ; CHECK: RET 0, implicit $rax
    %0:gpr(s32) = COPY $edi
    %1:gpr(s64) = G_ZEXT %0(s32)
    $rax = COPY %1(s64)
    RET 0, implicit $rax

...