[AArch64][SME] Add matrix register definitions and parsing support
SME introduces the ZA array, a new piece of architectural register state
consisting of a matrix of [SVLb x SVLb] bytes, where SVL is the
implementation defined Streaming SVE vector length and SVLb is the
number of 8-bit elements in a vector of SVL bits.
SME instructions consist of three types of matrix operands:
* Tiles: a ZA tile is a square, two-dimensional sub-array of elements
within the ZA array. These tiles make up the larger accumulator array
and the granularity varies based on the element size, i.e.
- ZAQ0..ZAQ15 (smallest tile granule)
- ZAD0..ZAD7
- ZAS0..ZAS3
- ZAH0..ZAH1
or ZAB0 (largest tile granule, single tile)
* Tile vectors: similar to regular tiles, but have an extra 'h' or 'v'
to tell how the vector at [reg+offset] is layed out in the tile,
horizontally or vertically. E.g. za1h.h or za15v.q, which corresponds
to vectors in registers ZAH1 and ZAQ15, respectively.
* Accumulator matrix: this is the entire accumulator array ZA.
This patch adds the register classes and related operands and parsing
for SME instructions operating on the accumulator array.
The ADDHA and ADDVA instructions which operate on tiles are also added
in this patch to make some use of the code added, later patches will
make use of the other operands introduced here.
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06
Co-authored by: Sander de Smalen (@sdesmalen)
Reviewed By: david-arm
Differential Revision: https://reviews.llvm.org/D105570
2021-07-14 10:01:19 +02:00
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//=- AArch64SMEInstrInfo.td - AArch64 SME Instructions -*- tablegen -*-----=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// AArch64 Scalable Matrix Extension (SME) Instruction definitions.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Add vector elements horizontally or vertically to ZA tile.
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//===----------------------------------------------------------------------===//
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let Predicates = [HasSME] in {
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def ADDHA_MPPZ_S : sme_add_vector_to_tile_u32<0b0, "addha">;
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def ADDVA_MPPZ_S : sme_add_vector_to_tile_u32<0b1, "addva">;
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}
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let Predicates = [HasSMEI64] in {
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def ADDHA_MPPZ_D : sme_add_vector_to_tile_u64<0b0, "addha">;
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def ADDVA_MPPZ_D : sme_add_vector_to_tile_u64<0b1, "addva">;
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}
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[AArch64][SME] Add outer product instructions
This patch adds support for the following outer product instructions:
* BFMOPA, BFMOPS, FMOPA, FMOPS, SMOPA, SMOPS, SUMOPA, SUMOPS, UMOPA,
UMOPS, USMOPA, USMOPS.
Depends on D105570.
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06
Reviewed By: david-arm
Differential Revision: https://reviews.llvm.org/D105571
2021-07-15 10:41:08 +02:00
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let Predicates = [HasSME] in {
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//===----------------------------------------------------------------------===//
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// Outer products
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//===----------------------------------------------------------------------===//
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defm BFMOPA_MPPZZ : sme_bf16_outer_product<0b0, "bfmopa">;
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defm BFMOPS_MPPZZ : sme_bf16_outer_product<0b1, "bfmops">;
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def FMOPA_MPPZZ_S : sme_outer_product_fp32<0b0, "fmopa">;
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def FMOPS_MPPZZ_S : sme_outer_product_fp32<0b1, "fmops">;
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}
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let Predicates = [HasSMEF64] in {
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def FMOPA_MPPZZ_D : sme_outer_product_fp64<0b0, "fmopa">;
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def FMOPS_MPPZZ_D : sme_outer_product_fp64<0b1, "fmops">;
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}
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let Predicates = [HasSME] in {
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defm FMOPAL_MPPZZ : sme_f16_outer_product<0b0, "fmopa">;
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defm FMOPSL_MPPZZ : sme_f16_outer_product<0b1, "fmops">;
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def SMOPA_MPPZZ_S : sme_int_outer_product_i32<0b000, "smopa">;
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def SMOPS_MPPZZ_S : sme_int_outer_product_i32<0b001, "smops">;
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def UMOPA_MPPZZ_S : sme_int_outer_product_i32<0b110, "umopa">;
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def UMOPS_MPPZZ_S : sme_int_outer_product_i32<0b111, "umops">;
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def SUMOPA_MPPZZ_S : sme_int_outer_product_i32<0b010, "sumopa">;
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def SUMOPS_MPPZZ_S : sme_int_outer_product_i32<0b011, "sumops">;
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def USMOPA_MPPZZ_S : sme_int_outer_product_i32<0b100, "usmopa">;
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def USMOPS_MPPZZ_S : sme_int_outer_product_i32<0b101, "usmops">;
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}
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let Predicates = [HasSMEI64] in {
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def SMOPA_MPPZZ_D : sme_int_outer_product_i64<0b000, "smopa">;
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def SMOPS_MPPZZ_D : sme_int_outer_product_i64<0b001, "smops">;
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def UMOPA_MPPZZ_D : sme_int_outer_product_i64<0b110, "umopa">;
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def UMOPS_MPPZZ_D : sme_int_outer_product_i64<0b111, "umops">;
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def SUMOPA_MPPZZ_D : sme_int_outer_product_i64<0b010, "sumopa">;
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def SUMOPS_MPPZZ_D : sme_int_outer_product_i64<0b011, "sumops">;
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def USMOPA_MPPZZ_D : sme_int_outer_product_i64<0b100, "usmopa">;
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def USMOPS_MPPZZ_D : sme_int_outer_product_i64<0b101, "usmops">;
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}
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2021-07-16 11:14:08 +02:00
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let Predicates = [HasSME] in {
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//===----------------------------------------------------------------------===//
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// Loads and stores
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//===----------------------------------------------------------------------===//
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defm LD1_MXIPXX : sme_mem_ld_ss<"ld1">;
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defm ST1_MXIPXX : sme_mem_st_ss<"st1">;
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} // End let Predicates = [HasSME]
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