2020-10-10 08:15:14 +02:00
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//===----------------------------------------------------------------------===//
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// Vector Instructions
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instructions
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//
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// Define all vector instructions defined in SX-Aurora TSUBASA Architecture
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// Guide here. As those mnemonics, we use mnemonics defined in Vector Engine
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// Assembly Language Reference Manual.
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//
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// Some instructions can update existing data by following instructions
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// sequence.
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//
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// lea %s0, 256
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// lea %s1, 128
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// lvl %s0
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// vbrd %v0, 2 # v0 = { 2, 2, 2, ..., 2, 2, 2 }
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// lvl %s1
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// vbrd %v0, 3 # v0 = { 3, 3, 3, ..., 3, 2, 2, 2, ..., 2, 2, 2 }
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//
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// In order to represent above with a virtual register, we defines instructions
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// with an additional base register and `_v` suffiex in mnemonic.
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//
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// lea t0, 256
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// lea t1, 128
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// lea t0
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// vbrd tv0, 2
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// lvl t1
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// vbrd_v tv1, 2, tv0
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//
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// We also have some instructions uses VL register with an pseudo VL value
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// with following suffixes in mnemonic.
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//
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// l: have an additional I32 register to represent the VL value.
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// L: have an additional VL register to represent the VL value.
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//===----------------------------------------------------------------------===//
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//-----------------------------------------------------------------------------
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// Section 8.9 - Vector Load/Store and Move Instructions
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//-----------------------------------------------------------------------------
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// Multiclass for VLD instructions
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let mayLoad = 1, hasSideEffects = 0, Uses = [VL] in
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multiclass VLDbm<string opcStr, bits<8>opc, RegisterClass RC, dag dag_in,
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string disEnc = ""> {
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let DisableEncoding = disEnc in
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def "" : RVM<opc, (outs RC:$vx), dag_in,
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!strconcat(opcStr, " $vx, $sy, $sz")>;
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let Constraints = "$vx = $base", DisableEncoding = disEnc#"$base",
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isCodeGenOnly = 1 in
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def _v : RVM<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
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!strconcat(opcStr, " $vx, $sy, $sz")>;
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}
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multiclass VLDlm<string opcStr, bits<8>opc, RegisterClass RC, dag dag_in> {
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defm "" : VLDbm<opcStr, opc, RC, dag_in>;
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let isCodeGenOnly = 1, VE_VLInUse = 1 in {
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defm l : VLDbm<opcStr, opc, RC, !con(dag_in, (ins I32:$vl)), "$vl,">;
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defm L : VLDbm<opcStr, opc, RC, !con(dag_in, (ins VLS:$vl)), "$vl,">;
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}
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}
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let VE_VLIndex = 3 in
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multiclass VLDtgm<string opcStr, bits<8>opc, RegisterClass RC> {
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defm rr : VLDlm<opcStr, opc, RC, (ins I64:$sy, I64:$sz)>;
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let cy = 0 in
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defm ir : VLDlm<opcStr, opc, RC, (ins simm7:$sy, I64:$sz)>;
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let cz = 0 in
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defm rz : VLDlm<opcStr, opc, RC, (ins I64:$sy, zero:$sz)>;
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let cy = 0, cz = 0 in
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defm iz : VLDlm<opcStr, opc, RC, (ins simm7:$sy, zero:$sz)>;
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}
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multiclass VLDm<string opcStr, bits<8>opc, RegisterClass RC> {
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let vc = 1 in defm "" : VLDtgm<opcStr, opc, RC>;
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let vc = 0 in defm NC : VLDtgm<opcStr#".nc", opc, RC>;
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}
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// Section 8.9.1 - VLD (Vector Load)
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defm VLD : VLDm<"vld", 0x81, V64>;
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// Section 8.9.2 - VLDU (Vector Load Upper)
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defm VLDU : VLDm<"vldu", 0x82, V64>;
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// Section 8.9.3 - VLDL (Vector Load Lower)
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defm VLDLSX : VLDm<"vldl.sx", 0x83, V64>;
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let cx = 1 in defm VLDLZX : VLDm<"vldl.zx", 0x83, V64>;
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// Section 8.9.4 - VLD2D (Vector Load 2D)
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defm VLD2D : VLDm<"vld2d", 0xc1, V64>;
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// Section 8.9.5 - VLDU2D (Vector Load Upper 2D)
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defm VLDU2D : VLDm<"vldu2d", 0xc2, V64>;
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// Section 8.9.6 - VLDL2D (Vector Load Lower 2D)
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defm VLDL2DSX : VLDm<"vldl2d.sx", 0xc3, V64>;
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let cx = 1 in defm VLDL2DZX : VLDm<"vldl2d.zx", 0xc3, V64>;
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// Multiclass for VST instructions
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let mayStore = 1, hasSideEffects = 0, Uses = [VL] in
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multiclass VSTbm<string opcStr, string argStr, bits<8>opc, dag dag_in> {
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def "" : RVM<opc, (outs), dag_in, !strconcat(opcStr, argStr)>;
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let DisableEncoding = "$vl", isCodeGenOnly = 1, VE_VLInUse = 1 in {
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def l : RVM<opc, (outs), !con(dag_in, (ins I32:$vl)),
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!strconcat(opcStr, argStr)>;
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def L : RVM<opc, (outs), !con(dag_in, (ins VLS:$vl)),
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!strconcat(opcStr, argStr)>;
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}
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}
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multiclass VSTmm<string opcStr, bits<8>opc, dag dag_in> {
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defm "" : VSTbm<opcStr, " $vx, $sy, $sz", opc, dag_in>;
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let m = ?, VE_VLWithMask = 1 in
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defm m : VSTbm<opcStr, " $vx, $sy, $sz, $m", opc, !con(dag_in, (ins VM:$m))>;
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}
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let VE_VLIndex = 3 in
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multiclass VSTtgm<string opcStr, bits<8>opc, RegisterClass RC> {
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defm rrv : VSTmm<opcStr, opc, (ins I64:$sy, I64:$sz, RC:$vx)>;
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let cy = 0 in
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defm irv : VSTmm<opcStr, opc, (ins simm7:$sy, I64:$sz, RC:$vx)>;
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let cz = 0 in
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defm rzv : VSTmm<opcStr, opc, (ins I64:$sy, zero:$sz, RC:$vx)>;
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let cy = 0, cz = 0 in
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defm izv : VSTmm<opcStr, opc, (ins simm7:$sy, zero:$sz, RC:$vx)>;
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}
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multiclass VSTm<string opcStr, bits<8>opc, RegisterClass RC> {
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let vc = 1, cx = 0 in defm "" : VSTtgm<opcStr, opc, RC>;
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let vc = 0, cx = 0 in defm NC : VSTtgm<opcStr#".nc", opc, RC>;
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let vc = 1, cx = 1 in defm OT : VSTtgm<opcStr#".ot", opc, RC>;
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let vc = 0, cx = 1 in defm NCOT : VSTtgm<opcStr#".nc.ot", opc, RC>;
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}
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// Section 8.9.7 - VST (Vector Store)
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defm VST : VSTm<"vst", 0x91, V64>;
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// Section 8.9.8 - VST (Vector Store Upper)
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defm VSTU : VSTm<"vstu", 0x92, V64>;
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// Section 8.9.9 - VSTL (Vector Store Lower)
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defm VSTL : VSTm<"vstl", 0x93, V64>;
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// Section 8.9.10 - VST2D (Vector Store 2D)
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defm VST2D : VSTm<"vst2d", 0xd1, V64>;
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// Section 8.9.11 - VSTU2D (Vector Store Upper 2D)
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defm VSTU2D : VSTm<"vstu2d", 0xd2, V64>;
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// Section 8.9.12 - VSTL2D (Vector Store Lower 2D)
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defm VSTL2D : VSTm<"vstl2d", 0xd3, V64>;
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2020-10-15 16:35:34 +02:00
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// Multiclass for VGT instructions
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let mayLoad = 1, hasSideEffects = 0, Uses = [VL] in
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multiclass VGTbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
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dag dag_in, string disEnc = ""> {
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let DisableEncoding = disEnc in
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def "" : RVM<opc, (outs RC:$vx), dag_in,
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!strconcat(opcStr, " $vx, ", argStr)>;
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let Constraints = "$vx = $base", DisableEncoding = disEnc#"$base",
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isCodeGenOnly = 1 in
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def _v : RVM<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
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!strconcat(opcStr, " $vx, ", argStr)>;
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}
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multiclass VGTlm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
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dag dag_in> {
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defm "" : VGTbm<opcStr, argStr, opc, RC, dag_in>;
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let isCodeGenOnly = 1, VE_VLInUse = 1 in {
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defm l : VGTbm<opcStr, argStr, opc, RC, !con(dag_in, (ins I32:$vl)),
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"$vl,">;
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defm L : VGTbm<opcStr, argStr, opc, RC, !con(dag_in, (ins VLS:$vl)),
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"$vl,">;
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}
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}
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multiclass VGTmm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
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dag dag_in> {
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defm "" : VGTlm<opcStr, argStr, opc, RC, dag_in>;
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let m = ?, VE_VLWithMask = 1 in
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defm m : VGTlm<opcStr, argStr#", $m", opc, RC, !con(dag_in, (ins VM:$m))>;
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}
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let VE_VLIndex = 4 in
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multiclass VGTlhm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
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dag dag_in> {
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defm rr : VGTmm<opcStr, argStr#", $sy, $sz", opc, RC,
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!con(dag_in, (ins I64:$sy, I64:$sz))>;
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let cy = 0 in
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defm ir : VGTmm<opcStr, argStr#", $sy, $sz", opc, RC,
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!con(dag_in, (ins simm7:$sy, I64:$sz))>;
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let cz = 0 in
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defm rz : VGTmm<opcStr, argStr#", $sy, $sz", opc, RC,
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!con(dag_in, (ins I64:$sy, zero:$sz))>;
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let cy = 0, cz = 0 in
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defm iz : VGTmm<opcStr, argStr#", $sy, $sz", opc, RC,
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!con(dag_in, (ins simm7:$sy, zero:$sz))>;
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}
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multiclass VGTtgm<string opcStr, bits<8>opc, RegisterClass RC> {
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let vy = ? in defm v : VGTlhm<opcStr, "$vy", opc, RC, (ins V64:$vy)>;
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let cs = 1, sw = ? in defm s : VGTlhm<opcStr, "$sw", opc, RC, (ins I64:$sw)>;
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}
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multiclass VGTm<string opcStr, bits<8>opc, RegisterClass RC> {
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let vc = 1 in defm "" : VGTtgm<opcStr, opc, RC>;
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let vc = 0 in defm NC : VGTtgm<opcStr#".nc", opc, RC>;
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}
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// Section 8.9.13 - VGT (Vector Gather)
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defm VGT : VGTm<"vgt", 0xa1, V64>;
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// Section 8.9.14 - VGTU (Vector Gather Upper)
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defm VGTU : VGTm<"vgtu", 0xa2, V64>;
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// Section 8.9.15 - VGTL (Vector Gather Lower)
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defm VGTLSX : VGTm<"vgtl.sx", 0xa3, V64>;
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let cx = 1 in defm VGTLZX : VGTm<"vgtl.zx", 0xa3, V64>;
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def : MnemonicAlias<"vgtl", "vgtl.zx">;
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def : MnemonicAlias<"vgtl.nc", "vgtl.zx.nc">;
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// Multiclass for VSC instructions
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let mayStore = 1, hasSideEffects = 0, Uses = [VL] in
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multiclass VSCbm<string opcStr, string argStr, bits<8>opc, dag dag_in> {
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def "" : RVM<opc, (outs), dag_in, !strconcat(opcStr, argStr)>;
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let DisableEncoding = "$vl", isCodeGenOnly = 1, VE_VLInUse = 1 in {
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def l : RVM<opc, (outs), !con(dag_in, (ins I32:$vl)),
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!strconcat(opcStr, argStr)>;
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def L : RVM<opc, (outs), !con(dag_in, (ins VLS:$vl)),
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!strconcat(opcStr, argStr)>;
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}
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}
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multiclass VSCmm<string opcStr, string argStr, bits<8>opc, dag dag_in> {
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defm "" : VSCbm<opcStr, argStr, opc, dag_in>;
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let m = ?, VE_VLWithMask = 1 in
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defm m : VSCbm<opcStr, argStr#", $m", opc, !con(dag_in, (ins VM:$m))>;
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}
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let VE_VLIndex = 4 in
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multiclass VSClhm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
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dag dag_in> {
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defm rrv : VSCmm<opcStr, " $vx, "#argStr#", $sy, $sz", opc,
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!con(dag_in, (ins I64:$sy, I64:$sz, RC:$vx))>;
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let cy = 0 in
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defm irv : VSCmm<opcStr, " $vx, "#argStr#", $sy, $sz", opc,
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!con(dag_in, (ins simm7:$sy, I64:$sz, RC:$vx))>;
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let cz = 0 in
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defm rzv : VSCmm<opcStr, " $vx, "#argStr#", $sy, $sz", opc,
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!con(dag_in, (ins I64:$sy, zero:$sz, RC:$vx))>;
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let cy = 0, cz = 0 in
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defm izv : VSCmm<opcStr, " $vx, "#argStr#", $sy, $sz", opc,
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!con(dag_in, (ins simm7:$sy, zero:$sz, RC:$vx))>;
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}
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multiclass VSCtgm<string opcStr, bits<8>opc, RegisterClass RC> {
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let vy = ? in defm v : VSClhm<opcStr, "$vy", opc, RC, (ins V64:$vy)>;
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let cs = 1, sw = ? in defm s : VSClhm<opcStr, "$sw", opc, RC, (ins I64:$sw)>;
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}
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multiclass VSCm<string opcStr, bits<8>opc, RegisterClass RC> {
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let vc = 1, cx = 0 in defm "" : VSCtgm<opcStr, opc, RC>;
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let vc = 0, cx = 0 in defm NC : VSCtgm<opcStr#".nc", opc, RC>;
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let vc = 1, cx = 1 in defm OT : VSCtgm<opcStr#".ot", opc, RC>;
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let vc = 0, cx = 1 in defm NCOT : VSCtgm<opcStr#".nc.ot", opc, RC>;
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}
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// Section 8.9.16 - VSC (Vector Scatter)
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defm VSC : VSCm<"vsc", 0xb1, V64>;
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// Section 8.9.17 - VSCU (Vector Scatter Upper)
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defm VSCU : VSCm<"vscu", 0xb2, V64>;
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// Section 8.9.18 - VSCL (Vector Scatter Lower)
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defm VSCL : VSCm<"vscl", 0xb3, V64>;
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// Section 8.9.19 - PFCHV (Prefetch Vector)
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let Uses = [VL] in
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multiclass PFCHVbm<string opcStr, string argStr, bits<8>opc, dag dag_in> {
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def "" : RVM<opc, (outs), dag_in, !strconcat(opcStr, argStr)>;
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let DisableEncoding = "$vl", isCodeGenOnly = 1, VE_VLInUse = 1 in {
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def l : RVM<opc, (outs), !con(dag_in, (ins I32:$vl)),
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!strconcat(opcStr, argStr)>;
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def L : RVM<opc, (outs), !con(dag_in, (ins VLS:$vl)),
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!strconcat(opcStr, argStr)>;
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}
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}
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let VE_VLIndex = 2 in
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multiclass PFCHVm<string opcStr, bits<8>opc> {
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defm rr : PFCHVbm<opcStr, " $sy, $sz", opc, (ins I64:$sy, I64:$sz)>;
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let cy = 0 in
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defm ir : PFCHVbm<opcStr, " $sy, $sz", opc, (ins simm7:$sy, I64:$sz)>;
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let cz = 0 in
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defm rz : PFCHVbm<opcStr, " $sy, $sz", opc, (ins I64:$sy, zero:$sz)>;
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let cy = 0, cz = 0 in
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defm iz : PFCHVbm<opcStr, " $sy, $sz", opc, (ins simm7:$sy, zero:$sz)>;
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}
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let vc = 1, vx = 0 in defm PFCHV : PFCHVm<"pfchv", 0x80>;
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let vc = 0, vx = 0 in defm PFCHVNC : PFCHVm<"pfchv.nc", 0x80>;
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