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llvm-mirror/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll

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Change the fast-isel-abort option from bool to int to enable "levels" Summary: Currently fast-isel-abort will only abort for regular instructions, and just warn for function calls, terminators, function arguments. There is already fast-isel-abort-args but nothing for calls and terminators. This change turns the fast-isel-abort options into an integer option, so that multiple levels of strictness can be defined. This will help no being surprised when the "abort" option indeed does not abort, and enables the possibility to write test that verifies that no intrinsics are forgotten by fast-isel. Reviewers: resistor, echristo Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D7941 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 230775
2015-02-27 19:32:11 +01:00
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
[PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support. We'd use VSX float comparison instruction instead of non-vsx float comparison instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is opened. If the target does not have corresponding VSX instruction comparison for some type, just copy VSX-related register to common float register class and use non-vsx comparison instruction. Differential Revision: https://reviews.llvm.org/D57078 llvm-svn: 352174
2019-01-25 08:24:59 +01:00
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64le-unknown-linux-gnu -mattr=+vsx | FileCheck %s --check-prefix=VSX
Introduce codegen for the Signal Processing Engine Summary: The Signal Processing Engine (SPE) is found on NXP/Freescale e500v1, e500v2, and several e200 cores. This adds support targeting the e500v2, as this is more common than the e500v1, and is in SoCs still on the market. This patch is very intrusive because the SPE is binary incompatible with the traditional FPU. After discussing with others, the cleanest solution was to make both SPE and FPU features on top of a base PowerPC subset, so all FPU instructions are now wrapped with HasFPU predicates. Supported by this are: * Code generation following the SPE ABI at the LLVM IR level (calling conventions) * Single- and Double-precision math at the level supported by the APU. Still to do: * Vector operations * SPE intrinsics As this changes the Callee-saved register list order, one test, which tests the precise generated code, was updated to account for the new register order. Reviewed by: nemanjai Differential Revision: https://reviews.llvm.org/D44830 llvm-svn: 337347
2018-07-18 06:25:10 +02:00
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc-unknown-linux-gnu -mcpu=e500 -mattr=spe | FileCheck %s --check-prefix=SPE
[PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support. We'd use VSX float comparison instruction instead of non-vsx float comparison instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is opened. If the target does not have corresponding VSX instruction comparison for some type, just copy VSX-related register to common float register class and use non-vsx comparison instruction. Differential Revision: https://reviews.llvm.org/D57078 llvm-svn: 352174
2019-01-25 08:24:59 +01:00
declare void @foo()
Clean up function attributes on PPC fast-isel tests. llvm-svn: 243079
2015-07-24 03:07:50 +02:00
define void @t1a(float %a) nounwind {
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
entry:
[PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support. We'd use VSX float comparison instruction instead of non-vsx float comparison instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is opened. If the target does not have corresponding VSX instruction comparison for some type, just copy VSX-related register to common float register class and use non-vsx comparison instruction. Differential Revision: https://reviews.llvm.org/D57078 llvm-svn: 352174
2019-01-25 08:24:59 +01:00
; ELF64-LABEL: @t1a
; SPE-LABEL: @t1a
; VSX-LABEL: @t1a
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
%cmp = fcmp oeq float %a, 0.000000e+00
; ELF64: addis
; ELF64: lfs
; ELF64: fcmpu
[PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support. We'd use VSX float comparison instruction instead of non-vsx float comparison instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is opened. If the target does not have corresponding VSX instruction comparison for some type, just copy VSX-related register to common float register class and use non-vsx comparison instruction. Differential Revision: https://reviews.llvm.org/D57078 llvm-svn: 352174
2019-01-25 08:24:59 +01:00
; VSX: addis
; VSX: lfs
; VSX: fcmpu
Introduce codegen for the Signal Processing Engine Summary: The Signal Processing Engine (SPE) is found on NXP/Freescale e500v1, e500v2, and several e200 cores. This adds support targeting the e500v2, as this is more common than the e500v1, and is in SoCs still on the market. This patch is very intrusive because the SPE is binary incompatible with the traditional FPU. After discussing with others, the cleanest solution was to make both SPE and FPU features on top of a base PowerPC subset, so all FPU instructions are now wrapped with HasFPU predicates. Supported by this are: * Code generation following the SPE ABI at the LLVM IR level (calling conventions) * Single- and Double-precision math at the level supported by the APU. Still to do: * Vector operations * SPE intrinsics As this changes the Callee-saved register list order, one test, which tests the precise generated code, was updated to account for the new register order. Reviewed by: nemanjai Differential Revision: https://reviews.llvm.org/D44830 llvm-svn: 337347
2018-07-18 06:25:10 +02:00
; SPE: efscmpeq
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
call void @foo()
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
Clean up function attributes on PPC fast-isel tests. llvm-svn: 243079
2015-07-24 03:07:50 +02:00
define void @t1b(float %a) nounwind {
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
entry:
[PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support. We'd use VSX float comparison instruction instead of non-vsx float comparison instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is opened. If the target does not have corresponding VSX instruction comparison for some type, just copy VSX-related register to common float register class and use non-vsx comparison instruction. Differential Revision: https://reviews.llvm.org/D57078 llvm-svn: 352174
2019-01-25 08:24:59 +01:00
; ELF64-LABEL: @t1b
; SPE-LABEL: @t1b
; VSX-LABEL: @t1b
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
%cmp = fcmp oeq float %a, -0.000000e+00
; ELF64: addis
; ELF64: lfs
; ELF64: fcmpu
[PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support. We'd use VSX float comparison instruction instead of non-vsx float comparison instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is opened. If the target does not have corresponding VSX instruction comparison for some type, just copy VSX-related register to common float register class and use non-vsx comparison instruction. Differential Revision: https://reviews.llvm.org/D57078 llvm-svn: 352174
2019-01-25 08:24:59 +01:00
; VSX: addis
; VSX: lfs
; VSX: fcmpu
; SPE: efscmpeq
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
call void @foo()
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
define void @t1c(float %a) nounwind {
entry:
; ELF64-LABEL: @t1c
; SPE-LABEL: @t1c
; VSX-LABEL: @t1c
%cmp = fcmp oeq float -0.000000e+00, %a
; ELF64: addis
; ELF64: lfs
; ELF64: fcmpu
; VSX: addis
; VSX: lfs
; VSX: fcmpu
Introduce codegen for the Signal Processing Engine Summary: The Signal Processing Engine (SPE) is found on NXP/Freescale e500v1, e500v2, and several e200 cores. This adds support targeting the e500v2, as this is more common than the e500v1, and is in SoCs still on the market. This patch is very intrusive because the SPE is binary incompatible with the traditional FPU. After discussing with others, the cleanest solution was to make both SPE and FPU features on top of a base PowerPC subset, so all FPU instructions are now wrapped with HasFPU predicates. Supported by this are: * Code generation following the SPE ABI at the LLVM IR level (calling conventions) * Single- and Double-precision math at the level supported by the APU. Still to do: * Vector operations * SPE intrinsics As this changes the Callee-saved register list order, one test, which tests the precise generated code, was updated to account for the new register order. Reviewed by: nemanjai Differential Revision: https://reviews.llvm.org/D44830 llvm-svn: 337347
2018-07-18 06:25:10 +02:00
; SPE: efscmpeq
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
call void @foo()
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
Clean up function attributes on PPC fast-isel tests. llvm-svn: 243079
2015-07-24 03:07:50 +02:00
define void @t2a(double %a) nounwind {
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
entry:
[PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support. We'd use VSX float comparison instruction instead of non-vsx float comparison instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is opened. If the target does not have corresponding VSX instruction comparison for some type, just copy VSX-related register to common float register class and use non-vsx comparison instruction. Differential Revision: https://reviews.llvm.org/D57078 llvm-svn: 352174
2019-01-25 08:24:59 +01:00
; ELF64-LABEL: @t2a
; SPE-LABEL: @t2a
; VSX-LABEL: @t2a
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
%cmp = fcmp oeq double %a, 0.000000e+00
; ELF64: addis
; ELF64: lfd
; ELF64: fcmpu
[PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support. We'd use VSX float comparison instruction instead of non-vsx float comparison instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is opened. If the target does not have corresponding VSX instruction comparison for some type, just copy VSX-related register to common float register class and use non-vsx comparison instruction. Differential Revision: https://reviews.llvm.org/D57078 llvm-svn: 352174
2019-01-25 08:24:59 +01:00
; VSX: addis
; VSX: lfd
; VSX: xscmpudp
Introduce codegen for the Signal Processing Engine Summary: The Signal Processing Engine (SPE) is found on NXP/Freescale e500v1, e500v2, and several e200 cores. This adds support targeting the e500v2, as this is more common than the e500v1, and is in SoCs still on the market. This patch is very intrusive because the SPE is binary incompatible with the traditional FPU. After discussing with others, the cleanest solution was to make both SPE and FPU features on top of a base PowerPC subset, so all FPU instructions are now wrapped with HasFPU predicates. Supported by this are: * Code generation following the SPE ABI at the LLVM IR level (calling conventions) * Single- and Double-precision math at the level supported by the APU. Still to do: * Vector operations * SPE intrinsics As this changes the Callee-saved register list order, one test, which tests the precise generated code, was updated to account for the new register order. Reviewed by: nemanjai Differential Revision: https://reviews.llvm.org/D44830 llvm-svn: 337347
2018-07-18 06:25:10 +02:00
; SPE: efdcmpeq
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
call void @foo()
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
Clean up function attributes on PPC fast-isel tests. llvm-svn: 243079
2015-07-24 03:07:50 +02:00
define void @t2b(double %a) nounwind {
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
entry:
[PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support. We'd use VSX float comparison instruction instead of non-vsx float comparison instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is opened. If the target does not have corresponding VSX instruction comparison for some type, just copy VSX-related register to common float register class and use non-vsx comparison instruction. Differential Revision: https://reviews.llvm.org/D57078 llvm-svn: 352174
2019-01-25 08:24:59 +01:00
; ELF64-LABEL: @t2b
; SPE-LABEL: @t2b
; VSX-LABEL: @t2b
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
%cmp = fcmp oeq double %a, -0.000000e+00
; ELF64: addis
; ELF64: lfd
; ELF64: fcmpu
[PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support. We'd use VSX float comparison instruction instead of non-vsx float comparison instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is opened. If the target does not have corresponding VSX instruction comparison for some type, just copy VSX-related register to common float register class and use non-vsx comparison instruction. Differential Revision: https://reviews.llvm.org/D57078 llvm-svn: 352174
2019-01-25 08:24:59 +01:00
; VSX: addis
; VSX: lfd
; VSX: xscmpudp
; SPE: efdcmpeq
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
call void @foo()
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
define void @t2c(double %a) nounwind {
entry:
; ELF64-LABEL: @t2c
; SPE-LABEL: @t2c
; VSX-LABEL: @t2c
%cmp = fcmp oeq double -0.000000e+00, %a
; ELF64: addis
; ELF64: lfd
; ELF64: fcmpu
; VSX: addis
; VSX: lfd
; VSX: xscmpudp
Introduce codegen for the Signal Processing Engine Summary: The Signal Processing Engine (SPE) is found on NXP/Freescale e500v1, e500v2, and several e200 cores. This adds support targeting the e500v2, as this is more common than the e500v1, and is in SoCs still on the market. This patch is very intrusive because the SPE is binary incompatible with the traditional FPU. After discussing with others, the cleanest solution was to make both SPE and FPU features on top of a base PowerPC subset, so all FPU instructions are now wrapped with HasFPU predicates. Supported by this are: * Code generation following the SPE ABI at the LLVM IR level (calling conventions) * Single- and Double-precision math at the level supported by the APU. Still to do: * Vector operations * SPE intrinsics As this changes the Callee-saved register list order, one test, which tests the precise generated code, was updated to account for the new register order. Reviewed by: nemanjai Differential Revision: https://reviews.llvm.org/D44830 llvm-svn: 337347
2018-07-18 06:25:10 +02:00
; SPE: efdcmpeq
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
call void @foo()
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
Clean up function attributes on PPC fast-isel tests. llvm-svn: 243079
2015-07-24 03:07:50 +02:00
define void @t4(i8 signext %a) nounwind {
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
entry:
[PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support. We'd use VSX float comparison instruction instead of non-vsx float comparison instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is opened. If the target does not have corresponding VSX instruction comparison for some type, just copy VSX-related register to common float register class and use non-vsx comparison instruction. Differential Revision: https://reviews.llvm.org/D57078 llvm-svn: 352174
2019-01-25 08:24:59 +01:00
; ELF64-LABEL: @t4
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
%cmp = icmp eq i8 %a, -1
; ELF64: extsb
; ELF64: cmpwi
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
call void @foo()
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
Clean up function attributes on PPC fast-isel tests. llvm-svn: 243079
2015-07-24 03:07:50 +02:00
define void @t5(i8 zeroext %a) nounwind {
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
entry:
[PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support. We'd use VSX float comparison instruction instead of non-vsx float comparison instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is opened. If the target does not have corresponding VSX instruction comparison for some type, just copy VSX-related register to common float register class and use non-vsx comparison instruction. Differential Revision: https://reviews.llvm.org/D57078 llvm-svn: 352174
2019-01-25 08:24:59 +01:00
; ELF64-LABEL: @t5
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
%cmp = icmp eq i8 %a, 1
; ELF64: extsb
; ELF64: cmpwi
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
call void @foo()
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
[PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support. We'd use VSX float comparison instruction instead of non-vsx float comparison instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is opened. If the target does not have corresponding VSX instruction comparison for some type, just copy VSX-related register to common float register class and use non-vsx comparison instruction. Differential Revision: https://reviews.llvm.org/D57078 llvm-svn: 352174
2019-01-25 08:24:59 +01:00
define void @t5a(i8 zeroext %a) nounwind {
entry:
; ELF64-LABEL: @t5a
%cmp = icmp eq i8 1, %a
; ELF64: extsb
; ELF64: cmpw
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
call void @foo()
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
Clean up function attributes on PPC fast-isel tests. llvm-svn: 243079
2015-07-24 03:07:50 +02:00
define void @t6(i16 signext %a) nounwind {
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
entry:
[PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support. We'd use VSX float comparison instruction instead of non-vsx float comparison instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is opened. If the target does not have corresponding VSX instruction comparison for some type, just copy VSX-related register to common float register class and use non-vsx comparison instruction. Differential Revision: https://reviews.llvm.org/D57078 llvm-svn: 352174
2019-01-25 08:24:59 +01:00
; ELF64-LABEL: @t6
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
%cmp = icmp eq i16 %a, -1
; ELF64: extsh
; ELF64: cmpwi
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
call void @foo()
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
Clean up function attributes on PPC fast-isel tests. llvm-svn: 243079
2015-07-24 03:07:50 +02:00
define void @t7(i16 zeroext %a) nounwind {
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
entry:
[PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support. We'd use VSX float comparison instruction instead of non-vsx float comparison instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is opened. If the target does not have corresponding VSX instruction comparison for some type, just copy VSX-related register to common float register class and use non-vsx comparison instruction. Differential Revision: https://reviews.llvm.org/D57078 llvm-svn: 352174
2019-01-25 08:24:59 +01:00
; ELF64-LABEL: @t7
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
%cmp = icmp eq i16 %a, 1
; ELF64: extsh
; ELF64: cmpwi
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
call void @foo()
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
[PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support. We'd use VSX float comparison instruction instead of non-vsx float comparison instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is opened. If the target does not have corresponding VSX instruction comparison for some type, just copy VSX-related register to common float register class and use non-vsx comparison instruction. Differential Revision: https://reviews.llvm.org/D57078 llvm-svn: 352174
2019-01-25 08:24:59 +01:00
define void @t7a(i16 zeroext %a) nounwind {
entry:
; ELF64-LABEL: @t7a
%cmp = icmp eq i16 1, %a
; ELF64: extsh
; ELF64: cmpw
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
call void @foo()
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
Clean up function attributes on PPC fast-isel tests. llvm-svn: 243079
2015-07-24 03:07:50 +02:00
define void @t8(i32 %a) nounwind {
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
entry:
[PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support. We'd use VSX float comparison instruction instead of non-vsx float comparison instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is opened. If the target does not have corresponding VSX instruction comparison for some type, just copy VSX-related register to common float register class and use non-vsx comparison instruction. Differential Revision: https://reviews.llvm.org/D57078 llvm-svn: 352174
2019-01-25 08:24:59 +01:00
; ELF64-LABEL: @t8
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
%cmp = icmp eq i32 %a, -1
; ELF64: cmpwi
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
call void @foo()
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
Clean up function attributes on PPC fast-isel tests. llvm-svn: 243079
2015-07-24 03:07:50 +02:00
define void @t9(i32 %a) nounwind {
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
entry:
[PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support. We'd use VSX float comparison instruction instead of non-vsx float comparison instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is opened. If the target does not have corresponding VSX instruction comparison for some type, just copy VSX-related register to common float register class and use non-vsx comparison instruction. Differential Revision: https://reviews.llvm.org/D57078 llvm-svn: 352174
2019-01-25 08:24:59 +01:00
; ELF64-LABEL: @t9
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
%cmp = icmp eq i32 %a, 1
; ELF64: cmpwi
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
call void @foo()
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
Clean up function attributes on PPC fast-isel tests. llvm-svn: 243079
2015-07-24 03:07:50 +02:00
define void @t10(i32 %a) nounwind {
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
entry:
[PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support. We'd use VSX float comparison instruction instead of non-vsx float comparison instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is opened. If the target does not have corresponding VSX instruction comparison for some type, just copy VSX-related register to common float register class and use non-vsx comparison instruction. Differential Revision: https://reviews.llvm.org/D57078 llvm-svn: 352174
2019-01-25 08:24:59 +01:00
; ELF64-LABEL: @t10
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
%cmp = icmp eq i32 %a, 384
; ELF64: cmpwi
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
call void @foo()
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
Clean up function attributes on PPC fast-isel tests. llvm-svn: 243079
2015-07-24 03:07:50 +02:00
define void @t11(i32 %a) nounwind {
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
entry:
[PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support. We'd use VSX float comparison instruction instead of non-vsx float comparison instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is opened. If the target does not have corresponding VSX instruction comparison for some type, just copy VSX-related register to common float register class and use non-vsx comparison instruction. Differential Revision: https://reviews.llvm.org/D57078 llvm-svn: 352174
2019-01-25 08:24:59 +01:00
; ELF64-LABEL: @t11
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
%cmp = icmp eq i32 %a, 4096
; ELF64: cmpwi
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
call void @foo()
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
[PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support. We'd use VSX float comparison instruction instead of non-vsx float comparison instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is opened. If the target does not have corresponding VSX instruction comparison for some type, just copy VSX-related register to common float register class and use non-vsx comparison instruction. Differential Revision: https://reviews.llvm.org/D57078 llvm-svn: 352174
2019-01-25 08:24:59 +01:00
define void @t11a(i32 %a) nounwind {
entry:
; ELF64-LABEL: @t11a
%cmp = icmp eq i32 4096, %a
; ELF64: cmpw
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
call void @foo()
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
Clean up function attributes on PPC fast-isel tests. llvm-svn: 243079
2015-07-24 03:07:50 +02:00
define void @t12(i8 %a) nounwind {
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
entry:
[PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support. We'd use VSX float comparison instruction instead of non-vsx float comparison instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is opened. If the target does not have corresponding VSX instruction comparison for some type, just copy VSX-related register to common float register class and use non-vsx comparison instruction. Differential Revision: https://reviews.llvm.org/D57078 llvm-svn: 352174
2019-01-25 08:24:59 +01:00
; ELF64-LABEL: @t12
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
%cmp = icmp ugt i8 %a, -113
[PowerPC] Enable printing instructions using aliases TableGen had been nicely generating code to print a number of instructions using shorter aliases (and PowerPC has plenty of short mnemonics), but we were not calling it. For some of the aliases we support in the parser, TableGen can't infer the "inverse" alias relationship, so there is still more to do. Thus, after some hours of updating test cases... llvm-svn: 235616
2015-04-23 20:30:38 +02:00
; ELF64: clrlwi
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
; ELF64: cmplwi
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
call void @foo()
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
define void @t13() nounwind ssp {
entry:
[PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support. We'd use VSX float comparison instruction instead of non-vsx float comparison instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is opened. If the target does not have corresponding VSX instruction comparison for some type, just copy VSX-related register to common float register class and use non-vsx comparison instruction. Differential Revision: https://reviews.llvm.org/D57078 llvm-svn: 352174
2019-01-25 08:24:59 +01:00
; ELF64-LABEL: @t13
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
%cmp = icmp slt i32 -123, -2147483648
; ELF64: li
; ELF64: lis
; ELF64: cmpw
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
ret void
if.end: ; preds = %entry
ret void
}
Clean up function attributes on PPC fast-isel tests. llvm-svn: 243079
2015-07-24 03:07:50 +02:00
define void @t14(i64 %a) nounwind {
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
entry:
[PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support. We'd use VSX float comparison instruction instead of non-vsx float comparison instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is opened. If the target does not have corresponding VSX instruction comparison for some type, just copy VSX-related register to common float register class and use non-vsx comparison instruction. Differential Revision: https://reviews.llvm.org/D57078 llvm-svn: 352174
2019-01-25 08:24:59 +01:00
; ELF64-LABEL: @t14
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
%cmp = icmp eq i64 %a, -1
; ELF64: cmpdi
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
call void @foo()
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
Clean up function attributes on PPC fast-isel tests. llvm-svn: 243079
2015-07-24 03:07:50 +02:00
define void @t15(i64 %a) nounwind {
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
entry:
[PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support. We'd use VSX float comparison instruction instead of non-vsx float comparison instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is opened. If the target does not have corresponding VSX instruction comparison for some type, just copy VSX-related register to common float register class and use non-vsx comparison instruction. Differential Revision: https://reviews.llvm.org/D57078 llvm-svn: 352174
2019-01-25 08:24:59 +01:00
; ELF64-LABEL: @t15
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
%cmp = icmp eq i64 %a, 1
; ELF64: cmpdi
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
call void @foo()
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
Clean up function attributes on PPC fast-isel tests. llvm-svn: 243079
2015-07-24 03:07:50 +02:00
define void @t16(i64 %a) nounwind {
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
entry:
[PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support. We'd use VSX float comparison instruction instead of non-vsx float comparison instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is opened. If the target does not have corresponding VSX instruction comparison for some type, just copy VSX-related register to common float register class and use non-vsx comparison instruction. Differential Revision: https://reviews.llvm.org/D57078 llvm-svn: 352174
2019-01-25 08:24:59 +01:00
; ELF64-LABEL: @t16
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
%cmp = icmp eq i64 %a, 384
; ELF64: cmpdi
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
call void @foo()
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
Clean up function attributes on PPC fast-isel tests. llvm-svn: 243079
2015-07-24 03:07:50 +02:00
define void @t17(i64 %a) nounwind {
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
entry:
[PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support. We'd use VSX float comparison instruction instead of non-vsx float comparison instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is opened. If the target does not have corresponding VSX instruction comparison for some type, just copy VSX-related register to common float register class and use non-vsx comparison instruction. Differential Revision: https://reviews.llvm.org/D57078 llvm-svn: 352174
2019-01-25 08:24:59 +01:00
; ELF64-LABEL: @t17
[PowerPC] Handle selection of compare instructions in fast-isel. Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
2013-08-30 05:16:48 +02:00
%cmp = icmp eq i64 %a, 32768
; Extra operand so we don't match on cmpdi.
; ELF64: cmpd {{[0-9]+}}
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
call void @foo()
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
[PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support. We'd use VSX float comparison instruction instead of non-vsx float comparison instruction if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and VSFRC correspondingly if VSX feature is opened. If the target does not have corresponding VSX instruction comparison for some type, just copy VSX-related register to common float register class and use non-vsx comparison instruction. Differential Revision: https://reviews.llvm.org/D57078 llvm-svn: 352174
2019-01-25 08:24:59 +01:00
define void @t17a(i64 %a) nounwind {
entry:
; ELF64-LABEL: @t17a
%cmp = icmp eq i64 32768, %a
; Extra operand so we don't match on cmpdi.
; ELF64: cmpd {{[0-9]+}}
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
call void @foo()
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
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