llvm-mirror/test/CodeGen/X86/sse-align-5.ll

; RUN: llc < %s -march=x86-64 | grep movaps | count 1

define <2 x i64> @bar(<2 x i64>* %p) nounwind {
  %t = load <2 x i64>, <2 x i64>* %p
  ret <2 x i64> %t
}
Eliminate more uses of llvm-as and llvm-dis. llvm-svn: 81290 2009-09-09 01:54:48 +02:00			`; RUN: llc < %s -march=x86-64 \| grep movaps \| count 1`
Implement initial memory alignment awareness for SSE instructions. Vector loads and stores that have a specified alignment of less than 16 bytes now use instructions that support misaligned memory references. llvm-svn: 40015 2007-07-18 22:23:34 +02:00
Add nounwind. llvm-svn: 50837 2008-05-08 00:59:08 +02:00			`define <2 x i64> @bar(<2 x i64>* %p) nounwind {`
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=\|:\|^)\sload (?:atomic )?(?:volatile )?(.?))(\| addrspace\(\d+\) )\($\| (?:%\|@\|null\|undef\|blockaddress\|getelementptr\|addrspacecast\|bitcast\|inttoptr\|\[\[[a-zA-Z]\|\{\{).$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794 2015-02-27 22:17:42 +01:00			`%t = load <2 x i64>, <2 x i64>* %p`
Implement initial memory alignment awareness for SSE instructions. Vector loads and stores that have a specified alignment of less than 16 bytes now use instructions that support misaligned memory references. llvm-svn: 40015 2007-07-18 22:23:34 +02:00			`ret <2 x i64> %t`
			`}`