2017-07-27 01:20:35 +02:00
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//==- HexagonFrameLowering.h - Define frame lowering for Hexagon -*- C++ -*-==//
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2011-12-12 22:14:40 +01:00
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//
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2019-01-19 09:50:56 +01:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2011-12-12 22:14:40 +01:00
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//
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//===----------------------------------------------------------------------===//
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2014-08-13 18:26:38 +02:00
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#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONFRAMELOWERING_H
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#define LLVM_LIB_TARGET_HEXAGON_HEXAGONFRAMELOWERING_H
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2011-12-12 22:14:40 +01:00
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#include "Hexagon.h"
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2016-02-12 23:53:35 +01:00
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#include "HexagonBlockRanges.h"
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2016-12-16 02:00:40 +01:00
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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2017-11-03 23:32:11 +01:00
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#include "llvm/CodeGen/TargetFrameLowering.h"
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2016-12-16 02:00:40 +01:00
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#include <vector>
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2011-12-12 22:14:40 +01:00
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namespace llvm {
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2017-07-27 01:20:35 +02:00
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class BitVector;
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2015-04-22 18:43:53 +02:00
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class HexagonInstrInfo;
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2015-04-23 18:05:39 +02:00
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class HexagonRegisterInfo;
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2017-07-27 01:20:35 +02:00
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class MachineFunction;
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class MachineInstr;
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class MachineRegisterInfo;
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class TargetRegisterClass;
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2015-04-22 18:43:53 +02:00
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2011-12-12 22:14:40 +01:00
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class HexagonFrameLowering : public TargetFrameLowering {
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public:
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Add support for Linux/Musl ABI
Differential revision: https://reviews.llvm.org/D72701
The patch adds a new option ABI for Hexagon. It primary deals with
the way variable arguments are passed and is use in the Hexagon Linux Musl
environment.
If a callee function has a variable argument list, it must perform the
following operations to set up its function prologue:
1. Determine the number of registers which could have been used for passing
unnamed arguments. This can be calculated by counting the number of
registers used for passing named arguments. For example, if the callee
function is as follows:
int foo(int a, ...){ ... }
... then register R0 is used to access the argument ' a '. The registers
available for passing unnamed arguments are R1, R2, R3, R4, and R5.
2. Determine the number and size of the named arguments on the stack.
3. If the callee has named arguments on the stack, it should copy all of these
arguments to a location below the current position on the stack, and the
difference should be the size of the register-saved area plus padding
(if any is necessary).
The register-saved area constitutes all the registers that could have
been used to pass unnamed arguments. If the number of registers forming
the register-saved area is odd, it requires 4 bytes of padding; if the
number is even, no padding is required. This is done to ensure an 8-byte
alignment on the stack. For example, if the callee is as follows:
int foo(int a, ...){ ... }
... then the named arguments should be copied to the following location:
current_position - 5 (for R1-R5) * 4 (bytes) - 4 (bytes of padding)
If the callee is as follows:
int foo(int a, int b, ...){ ... }
... then the named arguments should be copied to the following location:
current_position - 4 (for R2-R5) * 4 (bytes) - 0 (bytes of padding)
4. After any named arguments have been copied, copy all the registers that
could have been used to pass unnamed arguments on the stack. If the number
of registers is odd, leave 4 bytes of padding and then start copying them
on the stack; if the number is even, no padding is required. This
constitutes the register-saved area. If padding is required, ensure
that the start location of padding is 8-byte aligned. If no padding is
required, ensure that the start location of the on-stack copy of the
first register which might have a variable argument is 8-byte aligned.
5. Decrement the stack pointer by the size of register saved area plus the
padding. For example, if the callee is as follows:
int foo(int a, ...){ ... } ;
... then the decrement value should be the following:
5 (for R1-R5) * 4 (bytes) + 4 (bytes of padding) = 24 bytes
The decrement should be performed before the allocframe instruction.
Increment the stack-pointer back by the same amount before returning
from the function.
2019-12-27 20:03:01 +01:00
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// First register which could possibly hold a variable argument.
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int FirstVarArgSavedReg;
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2015-04-22 18:43:53 +02:00
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explicit HexagonFrameLowering()
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Use Align for TFL::TransientStackAlignment
Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: arsenm, dschuff, jyknight, sdardis, jvesely, nhaehnle, sbc100, jgravelle-google, hiraditya, aheejin, fedor.sergeev, jrtc27, atanasyan, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69216
llvm-svn: 375398
2019-10-21 10:31:25 +02:00
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: TargetFrameLowering(StackGrowsDown, Align(8), 0, Align::None(), true) {}
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2011-12-12 22:14:40 +01:00
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2015-04-23 18:05:39 +02:00
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// All of the prolog/epilog functionality, including saving and restoring
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// callee-saved registers is handled in emitPrologue. This is to have the
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// logic for shrink-wrapping in one place.
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[ShrinkWrap] Add (a simplified version) of shrink-wrapping.
This patch introduces a new pass that computes the safe point to insert the
prologue and epilogue of the function.
The interest is to find safe points that are cheaper than the entry and exits
blocks.
As an example and to avoid regressions to be introduce, this patch also
implements the required bits to enable the shrink-wrapping pass for AArch64.
** Context **
Currently we insert the prologue and epilogue of the method/function in the
entry and exits blocks. Although this is correct, we can do a better job when
those are not immediately required and insert them at less frequently executed
places.
The job of the shrink-wrapping pass is to identify such places.
** Motivating example **
Let us consider the following function that perform a call only in one branch of
a if:
define i32 @f(i32 %a, i32 %b) {
%tmp = alloca i32, align 4
%tmp2 = icmp slt i32 %a, %b
br i1 %tmp2, label %true, label %false
true:
store i32 %a, i32* %tmp, align 4
%tmp4 = call i32 @doSomething(i32 0, i32* %tmp)
br label %false
false:
%tmp.0 = phi i32 [ %tmp4, %true ], [ %a, %0 ]
ret i32 %tmp.0
}
On AArch64 this code generates (removing the cfi directives to ease
readabilities):
_f: ; @f
; BB#0:
stp x29, x30, [sp, #-16]!
mov x29, sp
sub sp, sp, #16 ; =16
cmp w0, w1
b.ge LBB0_2
; BB#1: ; %true
stur w0, [x29, #-4]
sub x1, x29, #4 ; =4
mov w0, wzr
bl _doSomething
LBB0_2: ; %false
mov sp, x29
ldp x29, x30, [sp], #16
ret
With shrink-wrapping we could generate:
_f: ; @f
; BB#0:
cmp w0, w1
b.ge LBB0_2
; BB#1: ; %true
stp x29, x30, [sp, #-16]!
mov x29, sp
sub sp, sp, #16 ; =16
stur w0, [x29, #-4]
sub x1, x29, #4 ; =4
mov w0, wzr
bl _doSomething
add sp, x29, #16 ; =16
ldp x29, x30, [sp], #16
LBB0_2: ; %false
ret
Therefore, we would pay the overhead of setting up/destroying the frame only if
we actually do the call.
** Proposed Solution **
This patch introduces a new machine pass that perform the shrink-wrapping
analysis (See the comments at the beginning of ShrinkWrap.cpp for more details).
It then stores the safe save and restore point into the MachineFrameInfo
attached to the MachineFunction.
This information is then used by the PrologEpilogInserter (PEI) to place the
related code at the right place. This pass runs right before the PEI.
Unlike the original paper of Chow from PLDI’88, this implementation of
shrink-wrapping does not use expensive data-flow analysis and does not need hack
to properly avoid frequently executed point. Instead, it relies on dominance and
loop properties.
The pass is off by default and each target can opt-in by setting the
EnableShrinkWrap boolean to true in their derived class of TargetPassConfig.
This setting can also be overwritten on the command line by using
-enable-shrink-wrap.
Before you try out the pass for your target, make sure you properly fix your
emitProlog/emitEpilog/adjustForXXX method to cope with basic blocks that are not
necessarily the entry block.
** Design Decisions **
1. ShrinkWrap is its own pass right now. It could frankly be merged into PEI but
for debugging and clarity I thought it was best to have its own file.
2. Right now, we only support one save point and one restore point. At some
point we can expand this to several save point and restore point, the impacted
component would then be:
- The pass itself: New algorithm needed.
- MachineFrameInfo: Hold a list or set of Save/Restore point instead of one
pointer.
- PEI: Should loop over the save point and restore point.
Anyhow, at least for this first iteration, I do not believe this is interesting
to support the complex cases. We should revisit that when we motivating
examples.
Differential Revision: http://reviews.llvm.org/D9210
<rdar://problem/3201744>
llvm-svn: 236507
2015-05-05 19:38:16 +02:00
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void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const
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override;
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2015-04-23 18:05:39 +02:00
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
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override {}
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2016-12-16 02:00:40 +01:00
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2018-11-09 19:16:24 +01:00
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bool enableCalleeSaveSkip(const MachineFunction &MF) const override;
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2015-04-23 18:05:39 +02:00
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bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const override {
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2015-04-22 18:43:53 +02:00
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return true;
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}
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2016-12-16 02:00:40 +01:00
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2015-04-23 18:05:39 +02:00
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bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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2017-08-10 18:17:32 +02:00
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MachineBasicBlock::iterator MI, std::vector<CalleeSavedInfo> &CSI,
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2015-04-23 18:05:39 +02:00
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const TargetRegisterInfo *TRI) const override {
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return true;
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}
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2017-06-30 23:21:40 +02:00
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bool hasReservedCallFrame(const MachineFunction &MF) const override {
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// We always reserve call frame as a part of the initial stack allocation.
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return true;
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}
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2017-07-27 01:20:35 +02:00
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2017-06-30 23:21:40 +02:00
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bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override {
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// Override this function to avoid calling hasFP before CSI is set
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// (the default implementation calls hasFP).
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return true;
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}
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2017-07-27 01:20:35 +02:00
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2016-03-31 20:33:38 +02:00
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MachineBasicBlock::iterator
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const override;
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2015-04-22 18:43:53 +02:00
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void processFunctionBeforeFrameFinalized(MachineFunction &MF,
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2016-02-12 19:19:53 +01:00
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RegScavenger *RS = nullptr) const override;
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2015-07-14 19:17:13 +02:00
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void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
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2016-02-12 19:19:53 +01:00
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RegScavenger *RS) const override;
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2015-04-23 18:05:39 +02:00
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bool targetHandlesStackFrameRounding() const override {
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return true;
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}
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2016-12-16 02:00:40 +01:00
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2015-08-15 04:32:35 +02:00
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int getFrameIndexReference(const MachineFunction &MF, int FI,
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2016-02-12 19:19:53 +01:00
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unsigned &FrameReg) const override;
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2014-04-29 09:58:16 +02:00
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bool hasFP(const MachineFunction &MF) const override;
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2015-04-22 18:43:53 +02:00
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const SpillSlot *getCalleeSavedSpillSlots(unsigned &NumEntries)
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2016-02-12 19:19:53 +01:00
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const override {
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2015-04-22 18:43:53 +02:00
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static const SpillSlot Offsets[] = {
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{ Hexagon::R17, -4 }, { Hexagon::R16, -8 }, { Hexagon::D8, -8 },
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{ Hexagon::R19, -12 }, { Hexagon::R18, -16 }, { Hexagon::D9, -16 },
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{ Hexagon::R21, -20 }, { Hexagon::R20, -24 }, { Hexagon::D10, -24 },
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{ Hexagon::R23, -28 }, { Hexagon::R22, -32 }, { Hexagon::D11, -32 },
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{ Hexagon::R25, -36 }, { Hexagon::R24, -40 }, { Hexagon::D12, -40 },
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{ Hexagon::R27, -44 }, { Hexagon::R26, -48 }, { Hexagon::D13, -48 }
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};
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NumEntries = array_lengthof(Offsets);
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return Offsets;
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}
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bool assignCalleeSavedSpillSlots(MachineFunction &MF,
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2015-04-23 18:05:39 +02:00
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const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI)
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const override;
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2015-04-22 18:43:53 +02:00
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bool needsAligna(const MachineFunction &MF) const;
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2015-10-19 20:30:27 +02:00
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const MachineInstr *getAlignaInstr(const MachineFunction &MF) const;
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2015-04-23 18:05:39 +02:00
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2015-10-19 19:46:01 +02:00
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void insertCFIInstructions(MachineFunction &MF) const;
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2015-04-23 18:05:39 +02:00
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private:
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2017-07-27 01:20:35 +02:00
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using CSIVect = std::vector<CalleeSavedInfo>;
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2015-04-23 18:05:39 +02:00
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void expandAlloca(MachineInstr *AI, const HexagonInstrInfo &TII,
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unsigned SP, unsigned CF) const;
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2016-03-24 21:20:07 +01:00
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void insertPrologueInBlock(MachineBasicBlock &MBB, bool PrologueStubs) const;
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2015-04-23 18:05:39 +02:00
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void insertEpilogueInBlock(MachineBasicBlock &MBB) const;
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2017-06-30 23:21:40 +02:00
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void insertAllocframe(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator InsertPt, unsigned NumBytes) const;
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2015-04-23 18:05:39 +02:00
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bool insertCSRSpillsInBlock(MachineBasicBlock &MBB, const CSIVect &CSI,
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2016-03-24 21:20:07 +01:00
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const HexagonRegisterInfo &HRI, bool &PrologueStubs) const;
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2015-04-23 18:05:39 +02:00
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bool insertCSRRestoresInBlock(MachineBasicBlock &MBB, const CSIVect &CSI,
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const HexagonRegisterInfo &HRI) const;
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2016-07-27 18:26:39 +02:00
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void updateEntryPaths(MachineFunction &MF, MachineBasicBlock &SaveB) const;
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bool updateExitPaths(MachineBasicBlock &MBB, MachineBasicBlock &RestoreB,
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2016-05-26 21:44:28 +02:00
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BitVector &DoneT, BitVector &DoneF, BitVector &Path) const;
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2015-10-19 19:46:01 +02:00
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void insertCFIInstructionsAt(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator At) const;
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2015-04-23 18:05:39 +02:00
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void adjustForCalleeSavedRegsSpillCall(MachineFunction &MF) const;
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2016-02-12 19:19:53 +01:00
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bool expandCopy(MachineBasicBlock &B, MachineBasicBlock::iterator It,
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MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
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SmallVectorImpl<unsigned> &NewRegs) const;
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bool expandStoreInt(MachineBasicBlock &B, MachineBasicBlock::iterator It,
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MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
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SmallVectorImpl<unsigned> &NewRegs) const;
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bool expandLoadInt(MachineBasicBlock &B, MachineBasicBlock::iterator It,
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MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
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SmallVectorImpl<unsigned> &NewRegs) const;
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bool expandStoreVecPred(MachineBasicBlock &B, MachineBasicBlock::iterator It,
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MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
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SmallVectorImpl<unsigned> &NewRegs) const;
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bool expandLoadVecPred(MachineBasicBlock &B, MachineBasicBlock::iterator It,
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MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
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SmallVectorImpl<unsigned> &NewRegs) const;
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bool expandStoreVec2(MachineBasicBlock &B, MachineBasicBlock::iterator It,
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MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
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SmallVectorImpl<unsigned> &NewRegs) const;
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bool expandLoadVec2(MachineBasicBlock &B, MachineBasicBlock::iterator It,
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MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
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SmallVectorImpl<unsigned> &NewRegs) const;
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bool expandStoreVec(MachineBasicBlock &B, MachineBasicBlock::iterator It,
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MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
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SmallVectorImpl<unsigned> &NewRegs) const;
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bool expandLoadVec(MachineBasicBlock &B, MachineBasicBlock::iterator It,
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MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
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SmallVectorImpl<unsigned> &NewRegs) const;
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bool expandSpillMacros(MachineFunction &MF,
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SmallVectorImpl<unsigned> &NewRegs) const;
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2015-04-23 18:05:39 +02:00
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2016-02-12 23:53:35 +01:00
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unsigned findPhysReg(MachineFunction &MF, HexagonBlockRanges::IndexRange &FIR,
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HexagonBlockRanges::InstrIndexMap &IndexMap,
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HexagonBlockRanges::RegToRangeMap &DeadMap,
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const TargetRegisterClass *RC) const;
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void optimizeSpillSlots(MachineFunction &MF,
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SmallVectorImpl<unsigned> &VRegs) const;
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2015-04-23 18:05:39 +02:00
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void findShrunkPrologEpilog(MachineFunction &MF, MachineBasicBlock *&PrologB,
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MachineBasicBlock *&EpilogB) const;
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2016-04-25 19:49:44 +02:00
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void addCalleeSaveRegistersAsImpOperand(MachineInstr *MI, const CSIVect &CSI,
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bool IsDef, bool IsKill) const;
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2017-06-30 23:21:40 +02:00
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bool shouldInlineCSR(const MachineFunction &MF, const CSIVect &CSI) const;
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bool useSpillFunction(const MachineFunction &MF, const CSIVect &CSI) const;
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bool useRestoreFunction(const MachineFunction &MF, const CSIVect &CSI) const;
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2016-08-01 19:15:30 +02:00
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bool mayOverflowFrameOffset(MachineFunction &MF) const;
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2011-12-12 22:14:40 +01:00
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};
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2016-12-16 02:00:40 +01:00
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} // end namespace llvm
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2011-12-12 22:14:40 +01:00
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2016-12-16 02:00:40 +01:00
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#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONFRAMELOWERING_H
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