llvm-mirror/test/CodeGen/X86/vec_set-9.ll

; RUN: llvm-as < %s | llc -march=x86-64 | grep movd | count 1
; RUN: llvm-as < %s | llc -march=x86-64 | grep {punpcklqdq.*%xmm0, %xmm0}

define <2 x i64> @test3(i64 %A) nounwind {
entry:
	%B = insertelement <2 x i64> undef, i64 %A, i32 1
	ret <2 x i64> %B
}
Teach SD some vector identities, allowing us to compile vec_set-9 into: _test3: movd %rdi, %xmm1 #IMPLICIT_DEF %xmm0 punpcklqdq %xmm1, %xmm0 ret instead of: _test3: #IMPLICIT_DEF %rax movd %rax, %xmm0 movd %rdi, %xmm1 punpcklqdq %xmm1, %xmm0 ret This is still not ideal. There is no reason to two xmm regs. llvm-svn: 48058 2008-03-09 00:43:36 +01:00			`; RUN: llvm-as < %s \| llc -march=x86-64 \| grep movd \| count 1`
make this test harder llvm-svn: 48061 2008-03-09 01:30:06 +01:00			`; RUN: llvm-as < %s \| llc -march=x86-64 \| grep {punpcklqdq.*%xmm0, %xmm0}`
Teach SD some vector identities, allowing us to compile vec_set-9 into: _test3: movd %rdi, %xmm1 #IMPLICIT_DEF %xmm0 punpcklqdq %xmm1, %xmm0 ret instead of: _test3: #IMPLICIT_DEF %rax movd %rax, %xmm0 movd %rdi, %xmm1 punpcklqdq %xmm1, %xmm0 ret This is still not ideal. There is no reason to two xmm regs. llvm-svn: 48058 2008-03-09 00:43:36 +01:00
Add nounwind. llvm-svn: 50837 2008-05-08 00:59:08 +02:00			`define <2 x i64> @test3(i64 %A) nounwind {`
Teach SD some vector identities, allowing us to compile vec_set-9 into: _test3: movd %rdi, %xmm1 #IMPLICIT_DEF %xmm0 punpcklqdq %xmm1, %xmm0 ret instead of: _test3: #IMPLICIT_DEF %rax movd %rax, %xmm0 movd %rdi, %xmm1 punpcklqdq %xmm1, %xmm0 ret This is still not ideal. There is no reason to two xmm regs. llvm-svn: 48058 2008-03-09 00:43:36 +01:00			`entry:`
			`%B = insertelement <2 x i64> undef, i64 %A, i32 1`
			`ret <2 x i64> %B`
			`}`