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llvm-mirror/test/CodeGen/X86/sse4a.ll

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Add SSE4A MOVNTSS/MOVNTSD instructions. llvm-svn: 156281
2012-05-07 07:36:19 +02:00
; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse4a | FileCheck %s
These tests used intrinsics with the wrong prototype. They weren't caught because the old verifier just checked that something "was a pointer", but not that the pointee was correct. llvm-svn: 157544
2012-05-27 21:35:41 +02:00
define void @test1(i8* %p, <4 x float> %a) nounwind optsize ssp {
Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions. This required light surgery on the assembler and disassembler because the instructions use an uncommon encoding. They are the only two instructions in x86 that use register operands and two immediates. llvm-svn: 157634
2012-05-29 21:05:25 +02:00
; CHECK: test1:
Add SSE4A MOVNTSS/MOVNTSD instructions. llvm-svn: 156281
2012-05-07 07:36:19 +02:00
; CHECK: movntss
These tests used intrinsics with the wrong prototype. They weren't caught because the old verifier just checked that something "was a pointer", but not that the pointee was correct. llvm-svn: 157544
2012-05-27 21:35:41 +02:00
tail call void @llvm.x86.sse4a.movnt.ss(i8* %p, <4 x float> %a) nounwind
Add SSE4A MOVNTSS/MOVNTSD instructions. llvm-svn: 156281
2012-05-07 07:36:19 +02:00
ret void
}
These tests used intrinsics with the wrong prototype. They weren't caught because the old verifier just checked that something "was a pointer", but not that the pointee was correct. llvm-svn: 157544
2012-05-27 21:35:41 +02:00
declare void @llvm.x86.sse4a.movnt.ss(i8*, <4 x float>)
Add SSE4A MOVNTSS/MOVNTSD instructions. llvm-svn: 156281
2012-05-07 07:36:19 +02:00
These tests used intrinsics with the wrong prototype. They weren't caught because the old verifier just checked that something "was a pointer", but not that the pointee was correct. llvm-svn: 157544
2012-05-27 21:35:41 +02:00
define void @test2(i8* %p, <2 x double> %a) nounwind optsize ssp {
Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions. This required light surgery on the assembler and disassembler because the instructions use an uncommon encoding. They are the only two instructions in x86 that use register operands and two immediates. llvm-svn: 157634
2012-05-29 21:05:25 +02:00
; CHECK: test2:
Add SSE4A MOVNTSS/MOVNTSD instructions. llvm-svn: 156281
2012-05-07 07:36:19 +02:00
; CHECK: movntsd
These tests used intrinsics with the wrong prototype. They weren't caught because the old verifier just checked that something "was a pointer", but not that the pointee was correct. llvm-svn: 157544
2012-05-27 21:35:41 +02:00
tail call void @llvm.x86.sse4a.movnt.sd(i8* %p, <2 x double> %a) nounwind
Add SSE4A MOVNTSS/MOVNTSD instructions. llvm-svn: 156281
2012-05-07 07:36:19 +02:00
ret void
}
These tests used intrinsics with the wrong prototype. They weren't caught because the old verifier just checked that something "was a pointer", but not that the pointee was correct. llvm-svn: 157544
2012-05-27 21:35:41 +02:00
declare void @llvm.x86.sse4a.movnt.sd(i8*, <2 x double>)
Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions. This required light surgery on the assembler and disassembler because the instructions use an uncommon encoding. They are the only two instructions in x86 that use register operands and two immediates. llvm-svn: 157634
2012-05-29 21:05:25 +02:00
define <2 x i64> @test3(<2 x i64> %x) nounwind uwtable ssp {
; CHECK: test3:
; CHECK: extrq
%1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %x, i8 3, i8 2)
ret <2 x i64> %1
}
declare <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64>, i8, i8) nounwind
define <2 x i64> @test4(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
; CHECK: test4:
; CHECK: extrq
%1 = bitcast <2 x i64> %y to <16 x i8>
%2 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %x, <16 x i8> %1) nounwind
ret <2 x i64> %2
}
declare <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64>, <16 x i8>) nounwind
define <2 x i64> @test5(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
; CHECK: test5:
; CHECK: insertq
%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %x, <2 x i64> %y, i8 5, i8 6)
ret <2 x i64> %1
}
declare <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64>, <2 x i64>, i8, i8) nounwind
define <2 x i64> @test6(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
; CHECK: test6:
; CHECK: insertq
%1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %x, <2 x i64> %y) nounwind
ret <2 x i64> %1
}
declare <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64>, <2 x i64>) nounwind
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