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llvm-mirror/test/MC/AMDGPU/sop1-err.s

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R600/SI: Initial support for assembler and inline assembly This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. llvm-svn: 234381
2015-04-08 03:09:26 +02:00
// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=SI %s 2>&1 | FileCheck %s
s_mov_b32 v1, s2
// CHECK: error: invalid operand for instruction
s_mov_b32 s1, v0
// CHECK: error: invalid operand for instruction
s_mov_b32 s[1:2], s0
// CHECK: error: invalid operand for instruction
s_mov_b32 s0, s[1:2]
// CHECK: error: invalid operand for instruction
s_mov_b32 s220, s0
// CHECK: error: invalid operand for instruction
s_mov_b32 s0, s220
// CHECK: error: invalid operand for instruction
s_mov_b64 s1, s[0:1]
// CHECK: error: invalid operand for instruction
s_mov_b64 s[0:1], s1
// CHECK: error: invalid operand for instruction
// Immediate greater than 32-bits
s_mov_b32 s1, 0xfffffffff
// CHECK: error: invalid immediate: only 32-bit values are legal
// Immediate greater than 32-bits
s_mov_b64 s[0:1], 0xfffffffff
// CHECK: error: invalid immediate: only 32-bit values are legal
// Out of range register
s_mov_b32 s
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