[NFC][InstCombine] Redundant masking before left-shift (PR42563)
alive proofs:
a,b: https://rise4fun.com/Alive/4zsf
c,d,e,f: https://rise4fun.com/Alive/RC49
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns.
Other than these 6 patterns, i can't think of any other
reasonable variants right now, although i'm sure they exist.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
llvm-svn: 365641
2019-07-10 17:08:06 +02:00
|
|
|
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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|
; RUN: opt %s -instcombine -S | FileCheck %s
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; If we have some pattern that leaves only some low bits set, and then performs
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; left-shift of those bits, if none of the bits that are left after the final
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; shift are modified by the mask, we can omit the mask.
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; There are many variants to this pattern:
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; a) (x & ((1 << maskNbits) - 1)) << shiftNbits
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; simplify to:
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; x << shiftNbits
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; iff (maskNbits+shiftNbits) u>= bitwidth(x)
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; Simple tests. We don't care about extra uses.
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declare void @use32(i32)
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|
define i32 @t0_basic(i32 %x, i32 %nbits) {
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|
; CHECK-LABEL: @t0_basic(
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|
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|
; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[NBITS:%.*]]
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|
; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], -1
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; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
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; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]]
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; CHECK-NEXT: call void @use32(i32 [[T0]])
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; CHECK-NEXT: call void @use32(i32 [[T1]])
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; CHECK-NEXT: call void @use32(i32 [[T2]])
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; CHECK-NEXT: call void @use32(i32 [[T3]])
|
[InstCombine] Dropping redundant masking before left-shift [0/5] (PR42563)
Summary:
If we have some pattern that leaves only some low bits set, and then performs
left-shift of those bits, if none of the bits that are left after the final
shift are modified by the mask, we can omit the mask.
There are many variants to this pattern:
a. `(x & ((1 << MaskShAmt) - 1)) << ShiftShAmt`
All these patterns can be simplified to just:
`x << ShiftShAmt`
iff:
a. `(MaskShAmt+ShiftShAmt) u>= bitwidth(x)`
alive proof:
a: https://rise4fun.com/Alive/wi9
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns,
since i have this general kind of pattern in hotpaths,
and it is not totally outlandish for bit-twiddling code.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
Reviewers: spatel, nikic, huihuiz, xbolva00
Reviewed By: xbolva00
Subscribers: efriedma, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64512
llvm-svn: 366535
2019-07-19 10:25:43 +02:00
|
|
|
; CHECK-NEXT: [[T4:%.*]] = shl i32 [[X]], [[T3]]
|
[NFC][InstCombine] Redundant masking before left-shift (PR42563)
alive proofs:
a,b: https://rise4fun.com/Alive/4zsf
c,d,e,f: https://rise4fun.com/Alive/RC49
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns.
Other than these 6 patterns, i can't think of any other
reasonable variants right now, although i'm sure they exist.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
llvm-svn: 365641
2019-07-10 17:08:06 +02:00
|
|
|
; CHECK-NEXT: ret i32 [[T4]]
|
|
|
|
|
;
|
|
|
|
|
%t0 = shl i32 1, %nbits
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|
%t1 = add nsw i32 %t0, -1
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|
|
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|
%t2 = and i32 %t1, %x
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|
%t3 = sub i32 32, %nbits
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|
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|
|
call void @use32(i32 %t0)
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|
call void @use32(i32 %t1)
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|
call void @use32(i32 %t2)
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|
call void @use32(i32 %t3)
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|
|
|
|
%t4 = shl i32 %t2, %t3
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|
|
ret i32 %t4
|
|
|
|
|
}
|
|
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|
|
define i32 @t1_bigger_shift(i32 %x, i32 %nbits) {
|
|
|
|
|
; CHECK-LABEL: @t1_bigger_shift(
|
|
|
|
|
; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[NBITS:%.*]]
|
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|
|
; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], -1
|
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|
|
|
; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
|
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|
|
; CHECK-NEXT: [[T3:%.*]] = sub i32 33, [[NBITS]]
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T0]])
|
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|
|
; CHECK-NEXT: call void @use32(i32 [[T1]])
|
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|
|
|
; CHECK-NEXT: call void @use32(i32 [[T2]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T3]])
|
[InstCombine] Dropping redundant masking before left-shift [0/5] (PR42563)
Summary:
If we have some pattern that leaves only some low bits set, and then performs
left-shift of those bits, if none of the bits that are left after the final
shift are modified by the mask, we can omit the mask.
There are many variants to this pattern:
a. `(x & ((1 << MaskShAmt) - 1)) << ShiftShAmt`
All these patterns can be simplified to just:
`x << ShiftShAmt`
iff:
a. `(MaskShAmt+ShiftShAmt) u>= bitwidth(x)`
alive proof:
a: https://rise4fun.com/Alive/wi9
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns,
since i have this general kind of pattern in hotpaths,
and it is not totally outlandish for bit-twiddling code.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
Reviewers: spatel, nikic, huihuiz, xbolva00
Reviewed By: xbolva00
Subscribers: efriedma, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64512
llvm-svn: 366535
2019-07-19 10:25:43 +02:00
|
|
|
; CHECK-NEXT: [[T4:%.*]] = shl i32 [[X]], [[T3]]
|
[NFC][InstCombine] Redundant masking before left-shift (PR42563)
alive proofs:
a,b: https://rise4fun.com/Alive/4zsf
c,d,e,f: https://rise4fun.com/Alive/RC49
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns.
Other than these 6 patterns, i can't think of any other
reasonable variants right now, although i'm sure they exist.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
llvm-svn: 365641
2019-07-10 17:08:06 +02:00
|
|
|
; CHECK-NEXT: ret i32 [[T4]]
|
|
|
|
|
;
|
|
|
|
|
%t0 = shl i32 1, %nbits
|
|
|
|
|
%t1 = add nsw i32 %t0, -1
|
|
|
|
|
%t2 = and i32 %t1, %x
|
|
|
|
|
%t3 = sub i32 33, %nbits ; subtracting from bitwidth+1
|
|
|
|
|
call void @use32(i32 %t0)
|
|
|
|
|
call void @use32(i32 %t1)
|
|
|
|
|
call void @use32(i32 %t2)
|
|
|
|
|
call void @use32(i32 %t3)
|
|
|
|
|
%t4 = shl i32 %t2, %t3
|
|
|
|
|
ret i32 %t4
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @t2_bigger_mask(i32 %x, i32 %nbits) {
|
|
|
|
|
; CHECK-LABEL: @t2_bigger_mask(
|
|
|
|
|
; CHECK-NEXT: [[T0:%.*]] = add i32 [[NBITS:%.*]], 1
|
|
|
|
|
; CHECK-NEXT: [[T1:%.*]] = shl i32 1, [[T0]]
|
|
|
|
|
; CHECK-NEXT: [[T2:%.*]] = add nsw i32 [[T1]], -1
|
|
|
|
|
; CHECK-NEXT: [[T3:%.*]] = and i32 [[T2]], [[X:%.*]]
|
|
|
|
|
; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]]
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T0]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T1]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T2]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T3]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T4]])
|
[InstCombine] Dropping redundant masking before left-shift [0/5] (PR42563)
Summary:
If we have some pattern that leaves only some low bits set, and then performs
left-shift of those bits, if none of the bits that are left after the final
shift are modified by the mask, we can omit the mask.
There are many variants to this pattern:
a. `(x & ((1 << MaskShAmt) - 1)) << ShiftShAmt`
All these patterns can be simplified to just:
`x << ShiftShAmt`
iff:
a. `(MaskShAmt+ShiftShAmt) u>= bitwidth(x)`
alive proof:
a: https://rise4fun.com/Alive/wi9
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns,
since i have this general kind of pattern in hotpaths,
and it is not totally outlandish for bit-twiddling code.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
Reviewers: spatel, nikic, huihuiz, xbolva00
Reviewed By: xbolva00
Subscribers: efriedma, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64512
llvm-svn: 366535
2019-07-19 10:25:43 +02:00
|
|
|
; CHECK-NEXT: [[T5:%.*]] = shl i32 [[X]], [[T4]]
|
[NFC][InstCombine] Redundant masking before left-shift (PR42563)
alive proofs:
a,b: https://rise4fun.com/Alive/4zsf
c,d,e,f: https://rise4fun.com/Alive/RC49
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns.
Other than these 6 patterns, i can't think of any other
reasonable variants right now, although i'm sure they exist.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
llvm-svn: 365641
2019-07-10 17:08:06 +02:00
|
|
|
; CHECK-NEXT: ret i32 [[T5]]
|
|
|
|
|
;
|
|
|
|
|
%t0 = add i32 %nbits, 1
|
|
|
|
|
%t1 = shl i32 1, %t0 ; shifting by nbits+1
|
|
|
|
|
%t2 = add nsw i32 %t1, -1
|
|
|
|
|
%t3 = and i32 %t2, %x
|
|
|
|
|
%t4 = sub i32 32, %nbits
|
|
|
|
|
call void @use32(i32 %t0)
|
|
|
|
|
call void @use32(i32 %t1)
|
|
|
|
|
call void @use32(i32 %t2)
|
|
|
|
|
call void @use32(i32 %t3)
|
|
|
|
|
call void @use32(i32 %t4)
|
|
|
|
|
%t5 = shl i32 %t3, %t4
|
|
|
|
|
ret i32 %t5
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; Vectors
|
|
|
|
|
|
|
|
|
|
declare void @use3xi32(<3 x i32>)
|
|
|
|
|
|
|
|
|
|
define <3 x i32> @t3_vec_splat(<3 x i32> %x, <3 x i32> %nbits) {
|
|
|
|
|
; CHECK-LABEL: @t3_vec_splat(
|
|
|
|
|
; CHECK-NEXT: [[T1:%.*]] = shl <3 x i32> <i32 1, i32 1, i32 1>, [[NBITS:%.*]]
|
|
|
|
|
; CHECK-NEXT: [[T2:%.*]] = add nsw <3 x i32> [[T1]], <i32 -1, i32 -1, i32 -1>
|
|
|
|
|
; CHECK-NEXT: [[T3:%.*]] = and <3 x i32> [[T2]], [[X:%.*]]
|
|
|
|
|
; CHECK-NEXT: [[T4:%.*]] = sub <3 x i32> <i32 32, i32 32, i32 32>, [[NBITS]]
|
|
|
|
|
; CHECK-NEXT: call void @use3xi32(<3 x i32> [[NBITS]])
|
|
|
|
|
; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T1]])
|
|
|
|
|
; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T2]])
|
|
|
|
|
; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T3]])
|
|
|
|
|
; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T4]])
|
[InstCombine] Dropping redundant masking before left-shift [0/5] (PR42563)
Summary:
If we have some pattern that leaves only some low bits set, and then performs
left-shift of those bits, if none of the bits that are left after the final
shift are modified by the mask, we can omit the mask.
There are many variants to this pattern:
a. `(x & ((1 << MaskShAmt) - 1)) << ShiftShAmt`
All these patterns can be simplified to just:
`x << ShiftShAmt`
iff:
a. `(MaskShAmt+ShiftShAmt) u>= bitwidth(x)`
alive proof:
a: https://rise4fun.com/Alive/wi9
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns,
since i have this general kind of pattern in hotpaths,
and it is not totally outlandish for bit-twiddling code.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
Reviewers: spatel, nikic, huihuiz, xbolva00
Reviewed By: xbolva00
Subscribers: efriedma, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64512
llvm-svn: 366535
2019-07-19 10:25:43 +02:00
|
|
|
; CHECK-NEXT: [[T5:%.*]] = shl <3 x i32> [[X]], [[T4]]
|
[NFC][InstCombine] Redundant masking before left-shift (PR42563)
alive proofs:
a,b: https://rise4fun.com/Alive/4zsf
c,d,e,f: https://rise4fun.com/Alive/RC49
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns.
Other than these 6 patterns, i can't think of any other
reasonable variants right now, although i'm sure they exist.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
llvm-svn: 365641
2019-07-10 17:08:06 +02:00
|
|
|
; CHECK-NEXT: ret <3 x i32> [[T5]]
|
|
|
|
|
;
|
|
|
|
|
%t0 = add <3 x i32> %nbits, <i32 0, i32 0, i32 0>
|
|
|
|
|
%t1 = shl <3 x i32> <i32 1, i32 1, i32 1>, %t0
|
|
|
|
|
%t2 = add nsw <3 x i32> %t1, <i32 -1, i32 -1, i32 -1>
|
|
|
|
|
%t3 = and <3 x i32> %t2, %x
|
|
|
|
|
%t4 = sub <3 x i32> <i32 32, i32 32, i32 32>, %nbits
|
|
|
|
|
call void @use3xi32(<3 x i32> %t0)
|
|
|
|
|
call void @use3xi32(<3 x i32> %t1)
|
|
|
|
|
call void @use3xi32(<3 x i32> %t2)
|
|
|
|
|
call void @use3xi32(<3 x i32> %t3)
|
|
|
|
|
call void @use3xi32(<3 x i32> %t4)
|
|
|
|
|
%t5 = shl <3 x i32> %t3, %t4
|
|
|
|
|
ret <3 x i32> %t5
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <3 x i32> @t4_vec_nonsplat(<3 x i32> %x, <3 x i32> %nbits) {
|
|
|
|
|
; CHECK-LABEL: @t4_vec_nonsplat(
|
|
|
|
|
; CHECK-NEXT: [[T0:%.*]] = add <3 x i32> [[NBITS:%.*]], <i32 -1, i32 0, i32 1>
|
|
|
|
|
; CHECK-NEXT: [[T1:%.*]] = shl <3 x i32> <i32 1, i32 1, i32 1>, [[T0]]
|
|
|
|
|
; CHECK-NEXT: [[T2:%.*]] = add nsw <3 x i32> [[T1]], <i32 -1, i32 -1, i32 -1>
|
|
|
|
|
; CHECK-NEXT: [[T3:%.*]] = and <3 x i32> [[T2]], [[X:%.*]]
|
|
|
|
|
; CHECK-NEXT: [[T4:%.*]] = sub <3 x i32> <i32 33, i32 32, i32 32>, [[NBITS]]
|
|
|
|
|
; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T0]])
|
|
|
|
|
; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T1]])
|
|
|
|
|
; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T2]])
|
|
|
|
|
; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T3]])
|
|
|
|
|
; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T4]])
|
[InstCombine] Dropping redundant masking before left-shift [0/5] (PR42563)
Summary:
If we have some pattern that leaves only some low bits set, and then performs
left-shift of those bits, if none of the bits that are left after the final
shift are modified by the mask, we can omit the mask.
There are many variants to this pattern:
a. `(x & ((1 << MaskShAmt) - 1)) << ShiftShAmt`
All these patterns can be simplified to just:
`x << ShiftShAmt`
iff:
a. `(MaskShAmt+ShiftShAmt) u>= bitwidth(x)`
alive proof:
a: https://rise4fun.com/Alive/wi9
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns,
since i have this general kind of pattern in hotpaths,
and it is not totally outlandish for bit-twiddling code.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
Reviewers: spatel, nikic, huihuiz, xbolva00
Reviewed By: xbolva00
Subscribers: efriedma, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64512
llvm-svn: 366535
2019-07-19 10:25:43 +02:00
|
|
|
; CHECK-NEXT: [[T5:%.*]] = shl <3 x i32> [[X]], [[T4]]
|
[NFC][InstCombine] Redundant masking before left-shift (PR42563)
alive proofs:
a,b: https://rise4fun.com/Alive/4zsf
c,d,e,f: https://rise4fun.com/Alive/RC49
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns.
Other than these 6 patterns, i can't think of any other
reasonable variants right now, although i'm sure they exist.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
llvm-svn: 365641
2019-07-10 17:08:06 +02:00
|
|
|
; CHECK-NEXT: ret <3 x i32> [[T5]]
|
|
|
|
|
;
|
|
|
|
|
%t0 = add <3 x i32> %nbits, <i32 -1, i32 0, i32 1>
|
|
|
|
|
%t1 = shl <3 x i32> <i32 1, i32 1, i32 1>, %t0
|
|
|
|
|
%t2 = add nsw <3 x i32> %t1, <i32 -1, i32 -1, i32 -1>
|
|
|
|
|
%t3 = and <3 x i32> %t2, %x
|
|
|
|
|
%t4 = sub <3 x i32> <i32 33, i32 32, i32 32>, %nbits
|
|
|
|
|
call void @use3xi32(<3 x i32> %t0)
|
|
|
|
|
call void @use3xi32(<3 x i32> %t1)
|
|
|
|
|
call void @use3xi32(<3 x i32> %t2)
|
|
|
|
|
call void @use3xi32(<3 x i32> %t3)
|
|
|
|
|
call void @use3xi32(<3 x i32> %t4)
|
|
|
|
|
%t5 = shl <3 x i32> %t3, %t4
|
|
|
|
|
ret <3 x i32> %t5
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <3 x i32> @t5_vec_undef(<3 x i32> %x, <3 x i32> %nbits) {
|
|
|
|
|
; CHECK-LABEL: @t5_vec_undef(
|
|
|
|
|
; CHECK-NEXT: [[T1:%.*]] = shl <3 x i32> <i32 1, i32 undef, i32 1>, [[NBITS:%.*]]
|
|
|
|
|
; CHECK-NEXT: [[T2:%.*]] = add nsw <3 x i32> [[T1]], <i32 -1, i32 undef, i32 -1>
|
|
|
|
|
; CHECK-NEXT: [[T3:%.*]] = and <3 x i32> [[T2]], [[X:%.*]]
|
|
|
|
|
; CHECK-NEXT: [[T4:%.*]] = sub <3 x i32> <i32 32, i32 undef, i32 32>, [[NBITS]]
|
|
|
|
|
; CHECK-NEXT: call void @use3xi32(<3 x i32> [[NBITS]])
|
|
|
|
|
; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T1]])
|
|
|
|
|
; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T2]])
|
|
|
|
|
; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T3]])
|
|
|
|
|
; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T4]])
|
[InstCombine] Dropping redundant masking before left-shift [0/5] (PR42563)
Summary:
If we have some pattern that leaves only some low bits set, and then performs
left-shift of those bits, if none of the bits that are left after the final
shift are modified by the mask, we can omit the mask.
There are many variants to this pattern:
a. `(x & ((1 << MaskShAmt) - 1)) << ShiftShAmt`
All these patterns can be simplified to just:
`x << ShiftShAmt`
iff:
a. `(MaskShAmt+ShiftShAmt) u>= bitwidth(x)`
alive proof:
a: https://rise4fun.com/Alive/wi9
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns,
since i have this general kind of pattern in hotpaths,
and it is not totally outlandish for bit-twiddling code.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
Reviewers: spatel, nikic, huihuiz, xbolva00
Reviewed By: xbolva00
Subscribers: efriedma, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64512
llvm-svn: 366535
2019-07-19 10:25:43 +02:00
|
|
|
; CHECK-NEXT: [[T5:%.*]] = shl <3 x i32> [[X]], [[T4]]
|
[NFC][InstCombine] Redundant masking before left-shift (PR42563)
alive proofs:
a,b: https://rise4fun.com/Alive/4zsf
c,d,e,f: https://rise4fun.com/Alive/RC49
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns.
Other than these 6 patterns, i can't think of any other
reasonable variants right now, although i'm sure they exist.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
llvm-svn: 365641
2019-07-10 17:08:06 +02:00
|
|
|
; CHECK-NEXT: ret <3 x i32> [[T5]]
|
|
|
|
|
;
|
|
|
|
|
%t0 = add <3 x i32> %nbits, <i32 0, i32 undef, i32 0>
|
|
|
|
|
%t1 = shl <3 x i32> <i32 1, i32 undef, i32 1>, %t0
|
|
|
|
|
%t2 = add nsw <3 x i32> %t1, <i32 -1, i32 undef, i32 -1>
|
|
|
|
|
%t3 = and <3 x i32> %t2, %x
|
|
|
|
|
%t4 = sub <3 x i32> <i32 32, i32 undef, i32 32>, %nbits
|
|
|
|
|
call void @use3xi32(<3 x i32> %t0)
|
|
|
|
|
call void @use3xi32(<3 x i32> %t1)
|
|
|
|
|
call void @use3xi32(<3 x i32> %t2)
|
|
|
|
|
call void @use3xi32(<3 x i32> %t3)
|
|
|
|
|
call void @use3xi32(<3 x i32> %t4)
|
|
|
|
|
%t5 = shl <3 x i32> %t3, %t4
|
|
|
|
|
ret <3 x i32> %t5
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; Commutativity
|
|
|
|
|
|
|
|
|
|
declare i32 @gen32()
|
|
|
|
|
|
|
|
|
|
define i32 @t6_commutativity0(i32 %nbits) {
|
|
|
|
|
; CHECK-LABEL: @t6_commutativity0(
|
|
|
|
|
; CHECK-NEXT: [[X:%.*]] = call i32 @gen32()
|
|
|
|
|
; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[NBITS:%.*]]
|
|
|
|
|
; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], -1
|
|
|
|
|
; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], [[T1]]
|
|
|
|
|
; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]]
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T0]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T1]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T2]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T3]])
|
[InstCombine] Dropping redundant masking before left-shift [0/5] (PR42563)
Summary:
If we have some pattern that leaves only some low bits set, and then performs
left-shift of those bits, if none of the bits that are left after the final
shift are modified by the mask, we can omit the mask.
There are many variants to this pattern:
a. `(x & ((1 << MaskShAmt) - 1)) << ShiftShAmt`
All these patterns can be simplified to just:
`x << ShiftShAmt`
iff:
a. `(MaskShAmt+ShiftShAmt) u>= bitwidth(x)`
alive proof:
a: https://rise4fun.com/Alive/wi9
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns,
since i have this general kind of pattern in hotpaths,
and it is not totally outlandish for bit-twiddling code.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
Reviewers: spatel, nikic, huihuiz, xbolva00
Reviewed By: xbolva00
Subscribers: efriedma, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64512
llvm-svn: 366535
2019-07-19 10:25:43 +02:00
|
|
|
; CHECK-NEXT: [[T4:%.*]] = shl i32 [[X]], [[T3]]
|
[NFC][InstCombine] Redundant masking before left-shift (PR42563)
alive proofs:
a,b: https://rise4fun.com/Alive/4zsf
c,d,e,f: https://rise4fun.com/Alive/RC49
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns.
Other than these 6 patterns, i can't think of any other
reasonable variants right now, although i'm sure they exist.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
llvm-svn: 365641
2019-07-10 17:08:06 +02:00
|
|
|
; CHECK-NEXT: ret i32 [[T4]]
|
|
|
|
|
;
|
|
|
|
|
%x = call i32 @gen32()
|
|
|
|
|
%t0 = shl i32 1, %nbits
|
|
|
|
|
%t1 = add nsw i32 %t0, -1
|
|
|
|
|
%t2 = and i32 %x, %t1 ; swapped
|
|
|
|
|
%t3 = sub i32 32, %nbits
|
|
|
|
|
call void @use32(i32 %t0)
|
|
|
|
|
call void @use32(i32 %t1)
|
|
|
|
|
call void @use32(i32 %t2)
|
|
|
|
|
call void @use32(i32 %t3)
|
|
|
|
|
%t4 = shl i32 %t2, %t3
|
|
|
|
|
ret i32 %t4
|
|
|
|
|
}
|
|
|
|
|
|
2019-07-10 21:58:13 +02:00
|
|
|
define i32 @t7_commutativity1(i32 %nbits0, i32 %nbits1) {
|
|
|
|
|
; CHECK-LABEL: @t7_commutativity1(
|
[NFC][InstCombine] Redundant masking before left-shift (PR42563)
alive proofs:
a,b: https://rise4fun.com/Alive/4zsf
c,d,e,f: https://rise4fun.com/Alive/RC49
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns.
Other than these 6 patterns, i can't think of any other
reasonable variants right now, although i'm sure they exist.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
llvm-svn: 365641
2019-07-10 17:08:06 +02:00
|
|
|
; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[NBITS0:%.*]]
|
|
|
|
|
; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], -1
|
|
|
|
|
; CHECK-NEXT: [[T2:%.*]] = shl i32 1, [[NBITS1:%.*]]
|
|
|
|
|
; CHECK-NEXT: [[T3:%.*]] = add nsw i32 [[T2]], -1
|
|
|
|
|
; CHECK-NEXT: [[T4:%.*]] = and i32 [[T3]], [[T1]]
|
|
|
|
|
; CHECK-NEXT: [[T5:%.*]] = sub i32 32, [[NBITS0]]
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T0]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T1]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T2]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T3]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T4]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T5]])
|
2019-07-10 18:54:13 +02:00
|
|
|
; CHECK-NEXT: [[T6:%.*]] = shl i32 [[T4]], [[T5]]
|
|
|
|
|
; CHECK-NEXT: ret i32 [[T6]]
|
[NFC][InstCombine] Redundant masking before left-shift (PR42563)
alive proofs:
a,b: https://rise4fun.com/Alive/4zsf
c,d,e,f: https://rise4fun.com/Alive/RC49
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns.
Other than these 6 patterns, i can't think of any other
reasonable variants right now, although i'm sure they exist.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
llvm-svn: 365641
2019-07-10 17:08:06 +02:00
|
|
|
;
|
|
|
|
|
%t0 = shl i32 1, %nbits0
|
|
|
|
|
%t1 = add nsw i32 %t0, -1
|
|
|
|
|
%t2 = shl i32 1, %nbits1
|
|
|
|
|
%t3 = add nsw i32 %t2, -1
|
|
|
|
|
%t4 = and i32 %t3, %t1 ; both hands of 'and' could be mask..
|
|
|
|
|
%t5 = sub i32 32, %nbits0
|
|
|
|
|
call void @use32(i32 %t0)
|
|
|
|
|
call void @use32(i32 %t1)
|
|
|
|
|
call void @use32(i32 %t2)
|
|
|
|
|
call void @use32(i32 %t3)
|
|
|
|
|
call void @use32(i32 %t4)
|
|
|
|
|
call void @use32(i32 %t5)
|
|
|
|
|
%t6 = shl i32 %t4, %t5
|
2019-07-10 18:54:13 +02:00
|
|
|
ret i32 %t6
|
[NFC][InstCombine] Redundant masking before left-shift (PR42563)
alive proofs:
a,b: https://rise4fun.com/Alive/4zsf
c,d,e,f: https://rise4fun.com/Alive/RC49
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns.
Other than these 6 patterns, i can't think of any other
reasonable variants right now, although i'm sure they exist.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
llvm-svn: 365641
2019-07-10 17:08:06 +02:00
|
|
|
}
|
2019-07-10 21:58:13 +02:00
|
|
|
define i32 @t8_commutativity2(i32 %nbits0, i32 %nbits1) {
|
|
|
|
|
; CHECK-LABEL: @t8_commutativity2(
|
[NFC][InstCombine] Redundant masking before left-shift (PR42563)
alive proofs:
a,b: https://rise4fun.com/Alive/4zsf
c,d,e,f: https://rise4fun.com/Alive/RC49
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns.
Other than these 6 patterns, i can't think of any other
reasonable variants right now, although i'm sure they exist.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
llvm-svn: 365641
2019-07-10 17:08:06 +02:00
|
|
|
; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[NBITS0:%.*]]
|
|
|
|
|
; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], -1
|
|
|
|
|
; CHECK-NEXT: [[T2:%.*]] = shl i32 1, [[NBITS1:%.*]]
|
|
|
|
|
; CHECK-NEXT: [[T3:%.*]] = add nsw i32 [[T2]], -1
|
|
|
|
|
; CHECK-NEXT: [[T4:%.*]] = and i32 [[T3]], [[T1]]
|
|
|
|
|
; CHECK-NEXT: [[T5:%.*]] = sub i32 32, [[NBITS1]]
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T0]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T1]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T2]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T3]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T4]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T5]])
|
[InstCombine] Dropping redundant masking before left-shift [0/5] (PR42563)
Summary:
If we have some pattern that leaves only some low bits set, and then performs
left-shift of those bits, if none of the bits that are left after the final
shift are modified by the mask, we can omit the mask.
There are many variants to this pattern:
a. `(x & ((1 << MaskShAmt) - 1)) << ShiftShAmt`
All these patterns can be simplified to just:
`x << ShiftShAmt`
iff:
a. `(MaskShAmt+ShiftShAmt) u>= bitwidth(x)`
alive proof:
a: https://rise4fun.com/Alive/wi9
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns,
since i have this general kind of pattern in hotpaths,
and it is not totally outlandish for bit-twiddling code.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
Reviewers: spatel, nikic, huihuiz, xbolva00
Reviewed By: xbolva00
Subscribers: efriedma, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64512
llvm-svn: 366535
2019-07-19 10:25:43 +02:00
|
|
|
; CHECK-NEXT: [[T6:%.*]] = shl i32 [[T1]], [[T5]]
|
2019-07-10 18:54:13 +02:00
|
|
|
; CHECK-NEXT: ret i32 [[T6]]
|
[NFC][InstCombine] Redundant masking before left-shift (PR42563)
alive proofs:
a,b: https://rise4fun.com/Alive/4zsf
c,d,e,f: https://rise4fun.com/Alive/RC49
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns.
Other than these 6 patterns, i can't think of any other
reasonable variants right now, although i'm sure they exist.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
llvm-svn: 365641
2019-07-10 17:08:06 +02:00
|
|
|
;
|
|
|
|
|
%t0 = shl i32 1, %nbits0
|
|
|
|
|
%t1 = add nsw i32 %t0, -1
|
|
|
|
|
%t2 = shl i32 1, %nbits1
|
|
|
|
|
%t3 = add nsw i32 %t2, -1
|
|
|
|
|
%t4 = and i32 %t3, %t1 ; both hands of 'and' could be mask..
|
|
|
|
|
%t5 = sub i32 32, %nbits1
|
|
|
|
|
call void @use32(i32 %t0)
|
|
|
|
|
call void @use32(i32 %t1)
|
|
|
|
|
call void @use32(i32 %t2)
|
|
|
|
|
call void @use32(i32 %t3)
|
|
|
|
|
call void @use32(i32 %t4)
|
|
|
|
|
call void @use32(i32 %t5)
|
|
|
|
|
%t6 = shl i32 %t4, %t5
|
2019-07-10 18:54:13 +02:00
|
|
|
ret i32 %t6
|
[NFC][InstCombine] Redundant masking before left-shift (PR42563)
alive proofs:
a,b: https://rise4fun.com/Alive/4zsf
c,d,e,f: https://rise4fun.com/Alive/RC49
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns.
Other than these 6 patterns, i can't think of any other
reasonable variants right now, although i'm sure they exist.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
llvm-svn: 365641
2019-07-10 17:08:06 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; Fast-math flags. We must not preserve them!
|
|
|
|
|
|
2019-07-10 21:58:13 +02:00
|
|
|
define i32 @t9_nuw(i32 %x, i32 %nbits) {
|
|
|
|
|
; CHECK-LABEL: @t9_nuw(
|
[NFC][InstCombine] Redundant masking before left-shift (PR42563)
alive proofs:
a,b: https://rise4fun.com/Alive/4zsf
c,d,e,f: https://rise4fun.com/Alive/RC49
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns.
Other than these 6 patterns, i can't think of any other
reasonable variants right now, although i'm sure they exist.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
llvm-svn: 365641
2019-07-10 17:08:06 +02:00
|
|
|
; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[NBITS:%.*]]
|
|
|
|
|
; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], -1
|
|
|
|
|
; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
|
|
|
|
|
; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]]
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T0]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T1]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T2]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T3]])
|
[InstCombine] Dropping redundant masking before left-shift [0/5] (PR42563)
Summary:
If we have some pattern that leaves only some low bits set, and then performs
left-shift of those bits, if none of the bits that are left after the final
shift are modified by the mask, we can omit the mask.
There are many variants to this pattern:
a. `(x & ((1 << MaskShAmt) - 1)) << ShiftShAmt`
All these patterns can be simplified to just:
`x << ShiftShAmt`
iff:
a. `(MaskShAmt+ShiftShAmt) u>= bitwidth(x)`
alive proof:
a: https://rise4fun.com/Alive/wi9
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns,
since i have this general kind of pattern in hotpaths,
and it is not totally outlandish for bit-twiddling code.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
Reviewers: spatel, nikic, huihuiz, xbolva00
Reviewed By: xbolva00
Subscribers: efriedma, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64512
llvm-svn: 366535
2019-07-19 10:25:43 +02:00
|
|
|
; CHECK-NEXT: [[T4:%.*]] = shl i32 [[X]], [[T3]]
|
[NFC][InstCombine] Redundant masking before left-shift (PR42563)
alive proofs:
a,b: https://rise4fun.com/Alive/4zsf
c,d,e,f: https://rise4fun.com/Alive/RC49
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns.
Other than these 6 patterns, i can't think of any other
reasonable variants right now, although i'm sure they exist.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
llvm-svn: 365641
2019-07-10 17:08:06 +02:00
|
|
|
; CHECK-NEXT: ret i32 [[T4]]
|
|
|
|
|
;
|
|
|
|
|
%t0 = shl i32 1, %nbits
|
|
|
|
|
%t1 = add nsw i32 %t0, -1
|
|
|
|
|
%t2 = and i32 %t1, %x
|
|
|
|
|
%t3 = sub i32 32, %nbits
|
|
|
|
|
call void @use32(i32 %t0)
|
|
|
|
|
call void @use32(i32 %t1)
|
|
|
|
|
call void @use32(i32 %t2)
|
|
|
|
|
call void @use32(i32 %t3)
|
|
|
|
|
%t4 = shl nuw i32 %t2, %t3
|
|
|
|
|
ret i32 %t4
|
|
|
|
|
}
|
|
|
|
|
|
2019-07-10 21:58:13 +02:00
|
|
|
define i32 @t10_nsw(i32 %x, i32 %nbits) {
|
|
|
|
|
; CHECK-LABEL: @t10_nsw(
|
[NFC][InstCombine] Redundant masking before left-shift (PR42563)
alive proofs:
a,b: https://rise4fun.com/Alive/4zsf
c,d,e,f: https://rise4fun.com/Alive/RC49
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns.
Other than these 6 patterns, i can't think of any other
reasonable variants right now, although i'm sure they exist.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
llvm-svn: 365641
2019-07-10 17:08:06 +02:00
|
|
|
; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[NBITS:%.*]]
|
|
|
|
|
; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], -1
|
|
|
|
|
; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
|
|
|
|
|
; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]]
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T0]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T1]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T2]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T3]])
|
[InstCombine] Dropping redundant masking before left-shift [0/5] (PR42563)
Summary:
If we have some pattern that leaves only some low bits set, and then performs
left-shift of those bits, if none of the bits that are left after the final
shift are modified by the mask, we can omit the mask.
There are many variants to this pattern:
a. `(x & ((1 << MaskShAmt) - 1)) << ShiftShAmt`
All these patterns can be simplified to just:
`x << ShiftShAmt`
iff:
a. `(MaskShAmt+ShiftShAmt) u>= bitwidth(x)`
alive proof:
a: https://rise4fun.com/Alive/wi9
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns,
since i have this general kind of pattern in hotpaths,
and it is not totally outlandish for bit-twiddling code.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
Reviewers: spatel, nikic, huihuiz, xbolva00
Reviewed By: xbolva00
Subscribers: efriedma, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64512
llvm-svn: 366535
2019-07-19 10:25:43 +02:00
|
|
|
; CHECK-NEXT: [[T4:%.*]] = shl i32 [[X]], [[T3]]
|
[NFC][InstCombine] Redundant masking before left-shift (PR42563)
alive proofs:
a,b: https://rise4fun.com/Alive/4zsf
c,d,e,f: https://rise4fun.com/Alive/RC49
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns.
Other than these 6 patterns, i can't think of any other
reasonable variants right now, although i'm sure they exist.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
llvm-svn: 365641
2019-07-10 17:08:06 +02:00
|
|
|
; CHECK-NEXT: ret i32 [[T4]]
|
|
|
|
|
;
|
|
|
|
|
%t0 = shl i32 1, %nbits
|
|
|
|
|
%t1 = add nsw i32 %t0, -1
|
|
|
|
|
%t2 = and i32 %t1, %x
|
|
|
|
|
%t3 = sub i32 32, %nbits
|
|
|
|
|
call void @use32(i32 %t0)
|
|
|
|
|
call void @use32(i32 %t1)
|
|
|
|
|
call void @use32(i32 %t2)
|
|
|
|
|
call void @use32(i32 %t3)
|
|
|
|
|
%t4 = shl nsw i32 %t2, %t3
|
|
|
|
|
ret i32 %t4
|
|
|
|
|
}
|
|
|
|
|
|
2019-07-10 21:58:13 +02:00
|
|
|
define i32 @t11_nuw_nsw(i32 %x, i32 %nbits) {
|
|
|
|
|
; CHECK-LABEL: @t11_nuw_nsw(
|
[NFC][InstCombine] Redundant masking before left-shift (PR42563)
alive proofs:
a,b: https://rise4fun.com/Alive/4zsf
c,d,e,f: https://rise4fun.com/Alive/RC49
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns.
Other than these 6 patterns, i can't think of any other
reasonable variants right now, although i'm sure they exist.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
llvm-svn: 365641
2019-07-10 17:08:06 +02:00
|
|
|
; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[NBITS:%.*]]
|
|
|
|
|
; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], -1
|
|
|
|
|
; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
|
|
|
|
|
; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]]
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T0]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T1]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T2]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T3]])
|
[InstCombine] Dropping redundant masking before left-shift [0/5] (PR42563)
Summary:
If we have some pattern that leaves only some low bits set, and then performs
left-shift of those bits, if none of the bits that are left after the final
shift are modified by the mask, we can omit the mask.
There are many variants to this pattern:
a. `(x & ((1 << MaskShAmt) - 1)) << ShiftShAmt`
All these patterns can be simplified to just:
`x << ShiftShAmt`
iff:
a. `(MaskShAmt+ShiftShAmt) u>= bitwidth(x)`
alive proof:
a: https://rise4fun.com/Alive/wi9
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns,
since i have this general kind of pattern in hotpaths,
and it is not totally outlandish for bit-twiddling code.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
Reviewers: spatel, nikic, huihuiz, xbolva00
Reviewed By: xbolva00
Subscribers: efriedma, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64512
llvm-svn: 366535
2019-07-19 10:25:43 +02:00
|
|
|
; CHECK-NEXT: [[T4:%.*]] = shl i32 [[X]], [[T3]]
|
[NFC][InstCombine] Redundant masking before left-shift (PR42563)
alive proofs:
a,b: https://rise4fun.com/Alive/4zsf
c,d,e,f: https://rise4fun.com/Alive/RC49
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns.
Other than these 6 patterns, i can't think of any other
reasonable variants right now, although i'm sure they exist.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
llvm-svn: 365641
2019-07-10 17:08:06 +02:00
|
|
|
; CHECK-NEXT: ret i32 [[T4]]
|
|
|
|
|
;
|
|
|
|
|
%t0 = shl i32 1, %nbits
|
|
|
|
|
%t1 = add nsw i32 %t0, -1
|
|
|
|
|
%t2 = and i32 %t1, %x
|
|
|
|
|
%t3 = sub i32 32, %nbits
|
|
|
|
|
call void @use32(i32 %t0)
|
|
|
|
|
call void @use32(i32 %t1)
|
|
|
|
|
call void @use32(i32 %t2)
|
|
|
|
|
call void @use32(i32 %t3)
|
|
|
|
|
%t4 = shl nuw nsw i32 %t2, %t3
|
|
|
|
|
ret i32 %t4
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; Negative tests
|
|
|
|
|
|
2019-07-10 21:58:13 +02:00
|
|
|
define i32 @n12_not_minus_one(i32 %x, i32 %nbits) {
|
|
|
|
|
; CHECK-LABEL: @n12_not_minus_one(
|
[NFC][InstCombine] Redundant masking before left-shift (PR42563)
alive proofs:
a,b: https://rise4fun.com/Alive/4zsf
c,d,e,f: https://rise4fun.com/Alive/RC49
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns.
Other than these 6 patterns, i can't think of any other
reasonable variants right now, although i'm sure they exist.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
llvm-svn: 365641
2019-07-10 17:08:06 +02:00
|
|
|
; CHECK-NEXT: [[T0:%.*]] = shl i32 2, [[NBITS:%.*]]
|
|
|
|
|
; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], -1
|
|
|
|
|
; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
|
|
|
|
|
; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]]
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T0]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T1]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T2]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T3]])
|
|
|
|
|
; CHECK-NEXT: [[T4:%.*]] = shl i32 [[T2]], [[T3]]
|
|
|
|
|
; CHECK-NEXT: ret i32 [[T4]]
|
|
|
|
|
;
|
|
|
|
|
%t0 = shl i32 2, %nbits ; shifting not '-1'
|
|
|
|
|
%t1 = add nsw i32 %t0, -1
|
|
|
|
|
%t2 = and i32 %t1, %x
|
|
|
|
|
%t3 = sub i32 32, %nbits
|
|
|
|
|
call void @use32(i32 %t0)
|
|
|
|
|
call void @use32(i32 %t1)
|
|
|
|
|
call void @use32(i32 %t2)
|
|
|
|
|
call void @use32(i32 %t3)
|
|
|
|
|
%t4 = shl i32 %t2, %t3
|
|
|
|
|
ret i32 %t4
|
|
|
|
|
}
|
|
|
|
|
|
2019-07-10 21:58:13 +02:00
|
|
|
define i32 @n13_not_minus_one(i32 %x, i32 %nbits) {
|
|
|
|
|
; CHECK-LABEL: @n13_not_minus_one(
|
[NFC][InstCombine] Redundant masking before left-shift (PR42563)
alive proofs:
a,b: https://rise4fun.com/Alive/4zsf
c,d,e,f: https://rise4fun.com/Alive/RC49
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns.
Other than these 6 patterns, i can't think of any other
reasonable variants right now, although i'm sure they exist.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
llvm-svn: 365641
2019-07-10 17:08:06 +02:00
|
|
|
; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[NBITS:%.*]]
|
|
|
|
|
; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], 2147483647
|
|
|
|
|
; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
|
|
|
|
|
; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]]
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T0]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T1]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T2]])
|
|
|
|
|
; CHECK-NEXT: call void @use32(i32 [[T3]])
|
|
|
|
|
; CHECK-NEXT: [[T4:%.*]] = shl i32 [[T2]], [[T3]]
|
|
|
|
|
; CHECK-NEXT: ret i32 [[T4]]
|
|
|
|
|
;
|
|
|
|
|
%t0 = shl i32 1, %nbits
|
|
|
|
|
%t1 = add nsw i32 %t0, 2147483647 ; adding not '-1'
|
|
|
|
|
%t2 = and i32 %t1, %x
|
|
|
|
|
%t3 = sub i32 32, %nbits
|
|
|
|
|
call void @use32(i32 %t0)
|
|
|
|
|
call void @use32(i32 %t1)
|
|
|
|
|
call void @use32(i32 %t2)
|
|
|
|
|
call void @use32(i32 %t3)
|
|
|
|
|
%t4 = shl i32 %t2, %t3
|
|
|
|
|
ret i32 %t4
|
|
|
|
|
}
|