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llvm-mirror/test/CodeGen/X86/2009-05-08-InlineAsmIOffset.ll

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Rewrite some tests with FileCHeck in X86 codegen - Revise previous patches of the same purpose by fixing *) grep <PA> | not grep <PB> semantically is not the same as CHECK: <PA>{{^<PB>.*$}} as the former will check all occurrences of <PA> while the later only check the first match. As the result, CHECK needs putting in all place where <PA> occurs. *) grep <PA> | count <N> needs a final CHECK-NOT of the same pattern. (As 'CHECK-<N>' is proposed for discussion, converting 'grep | count <N>' where N > 1 is postponed.) llvm-svn: 180742
2013-04-30 00:41:29 +02:00
; RUN: llc < %s -relocation-model=static | FileCheck %s
Fix PR4152: asm constraint validation happens before dag combine, so we need to work a bit to combine things like (x+c1+c2) into x+c3. llvm-svn: 71232
2009-05-08 20:23:14 +02:00
; PR4152
Rewrite some tests with FileCHeck in X86 codegen - Revise previous patches of the same purpose by fixing *) grep <PA> | not grep <PB> semantically is not the same as CHECK: <PA>{{^<PB>.*$}} as the former will check all occurrences of <PA> while the later only check the first match. As the result, CHECK needs putting in all place where <PA> occurs. *) grep <PA> | count <N> needs a final CHECK-NOT of the same pattern. (As 'CHECK-<N>' is proposed for discussion, converting 'grep | count <N>' where N > 1 is postponed.) llvm-svn: 180742
2013-04-30 00:41:29 +02:00
; CHECK: {{1: ._pv_cpu_ops[+]8}}
; CHECK: {{2: ._G}}
Fix PR4152: asm constraint validation happens before dag combine, so we need to work a bit to combine things like (x+c1+c2) into x+c3. llvm-svn: 71232
2009-05-08 20:23:14 +02:00
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin9.6"
%struct.pv_cpu_ops = type { i32, [2 x i32] }
@pv_cpu_ops = external global %struct.pv_cpu_ops ; <%struct.pv_cpu_ops*> [#uses=1]
@G = external global i32 ; <i32*> [#uses=1]
define void @x() nounwind {
entry:
tail call void asm sideeffect "1: $0", "i,~{dirflag},~{fpsr},~{flags}"(i32* getelementptr (%struct.pv_cpu_ops* @pv_cpu_ops, i32 0, i32 1, i32 1)) nounwind
tail call void asm sideeffect "2: $0", "i,~{dirflag},~{fpsr},~{flags}"(i32* @G) nounwind
ret void
}
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