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llvm-mirror/test/CodeGen/AArch64/arm64-fast-isel-call.ll

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[FastISel][AArch64] Implement the FastLowerArguments hook. This implements basic argument lowering for AArch64 in FastISel. It only handles a small subset of the C calling convention. It supports simple arguments that can be passed in GPR and FPR registers. This should cover most of the trivial cases without falling back to SelectionDAG. This fixes <rdar://problem/17890986>. llvm-svn: 214846
2014-08-05 07:43:48 +02:00
; RUN: llc -O0 -fast-isel-abort -fast-isel-abort-args -code-model=small -mtriple=arm64-apple-darwin < %s | FileCheck %s
; RUN: llc -O0 -fast-isel-abort -fast-isel-abort-args -code-model=large -mtriple=arm64-apple-darwin < %s | FileCheck %s --check-prefix=LARGE
; RUN: llc -O0 -fast-isel-abort -fast-isel-abort-args -code-model=small -mtriple=aarch64_be-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-BE
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
define void @call0() nounwind {
entry:
ret void
}
define void @foo0() nounwind {
entry:
[FastISel][AArch64] Add MachO large code model support for function calls. Currently the large code model for MachO uses the GOT to make function calls. Emit the required adrp and ldr instructions to load the address from the GOT. Related to <rdar://problem/17733076>. llvm-svn: 214381
2014-07-31 06:10:40 +02:00
; CHECK-LABEL: foo0
; CHECK: bl _call0
; LARGE-LABEL: foo0
; LARGE: adrp [[REG0:x[0-9]+]], _call0@GOTPAGE
; LARGE: ldr [[REG1:x[0-9]+]], {{\[}}[[REG0]], _call0@GOTPAGEOFF{{\]}}
; LARGE-NEXT: blr [[REG1]]
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
call void @call0()
ret void
}
define i32 @call1(i32 %a) nounwind {
entry:
%a.addr = alloca i32, align 4
store i32 %a, i32* %a.addr, align 4
%tmp = load i32* %a.addr, align 4
ret i32 %tmp
}
define i32 @foo1(i32 %a) nounwind {
entry:
[FastISel][AArch64] Add MachO large code model support for function calls. Currently the large code model for MachO uses the GOT to make function calls. Emit the required adrp and ldr instructions to load the address from the GOT. Related to <rdar://problem/17733076>. llvm-svn: 214381
2014-07-31 06:10:40 +02:00
; CHECK-LABEL: foo1
; CHECK: stur w0, [x29, #-4]
; CHECK-NEXT: ldur w0, [x29, #-4]
; CHECK-NEXT: bl _call1
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
%a.addr = alloca i32, align 4
store i32 %a, i32* %a.addr, align 4
%tmp = load i32* %a.addr, align 4
%call = call i32 @call1(i32 %tmp)
ret i32 %call
}
define i32 @sext_(i8 %a, i16 %b) nounwind {
entry:
[FastISel][AArch64] Add MachO large code model support for function calls. Currently the large code model for MachO uses the GOT to make function calls. Emit the required adrp and ldr instructions to load the address from the GOT. Related to <rdar://problem/17733076>. llvm-svn: 214381
2014-07-31 06:10:40 +02:00
; CHECK-LABEL: @sext_
; CHECK: sxtb w0, w0
; CHECK: sxth w1, w1
; CHECK: bl _foo_sext_
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
call void @foo_sext_(i8 signext %a, i16 signext %b)
ret i32 0
}
declare void @foo_sext_(i8 %a, i16 %b)
define i32 @zext_(i8 %a, i16 %b) nounwind {
entry:
[FastISel][AArch64] Add MachO large code model support for function calls. Currently the large code model for MachO uses the GOT to make function calls. Emit the required adrp and ldr instructions to load the address from the GOT. Related to <rdar://problem/17733076>. llvm-svn: 214381
2014-07-31 06:10:40 +02:00
; CHECK-LABEL: @zext_
; CHECK: uxtb w0, w0
; CHECK: uxth w1, w1
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
call void @foo_zext_(i8 zeroext %a, i16 zeroext %b)
ret i32 0
}
declare void @foo_zext_(i8 %a, i16 %b)
define i32 @t1(i32 %argc, i8** nocapture %argv) {
entry:
[FastISel][AArch64] Add MachO large code model support for function calls. Currently the large code model for MachO uses the GOT to make function calls. Emit the required adrp and ldr instructions to load the address from the GOT. Related to <rdar://problem/17733076>. llvm-svn: 214381
2014-07-31 06:10:40 +02:00
; CHECK-LABEL: @t1
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
; The last parameter will be passed on stack via i8.
[FastISel][AArch64] Add MachO large code model support for function calls. Currently the large code model for MachO uses the GOT to make function calls. Emit the required adrp and ldr instructions to load the address from the GOT. Related to <rdar://problem/17733076>. llvm-svn: 214381
2014-07-31 06:10:40 +02:00
; CHECK: strb w{{[0-9]+}}, [sp]
; CHECK: bl _bar
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
%call = call i32 @bar(i8 zeroext 0, i8 zeroext -8, i8 zeroext -69, i8 zeroext 28, i8 zeroext 40, i8 zeroext -70, i8 zeroext 28, i8 zeroext 39, i8 zeroext -41)
ret i32 0
}
declare i32 @bar(i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext)
; Test materialization of integers. Target-independent selector handles this.
define i32 @t2() {
entry:
[FastISel][AArch64] Add MachO large code model support for function calls. Currently the large code model for MachO uses the GOT to make function calls. Emit the required adrp and ldr instructions to load the address from the GOT. Related to <rdar://problem/17733076>. llvm-svn: 214381
2014-07-31 06:10:40 +02:00
; CHECK-LABEL: @t2
; CHECK: movz x0, #0
; CHECK: orr w1, wzr, #0xfffffff8
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x3ff
; CHECK: orr w[[REG2:[0-9]+]], wzr, #0x2
; CHECK: movz w[[REG3:[0-9]+]], #0
; CHECK: orr w[[REG4:[0-9]+]], wzr, #0x1
; CHECK: uxth w2, w[[REG]]
; CHECK: sxtb w3, w[[REG2]]
; CHECK: and w4, w[[REG3]], #0x1
; CHECK: and w5, w[[REG4]], #0x1
; CHECK: bl _func2
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
%call = call i32 @func2(i64 zeroext 0, i32 signext -8, i16 zeroext 1023, i8 signext -254, i1 zeroext 0, i1 zeroext 1)
ret i32 0
}
declare i32 @func2(i64 zeroext, i32 signext, i16 zeroext, i8 signext, i1 zeroext, i1 zeroext)
[ARM64-BE] Teach fast-isel about how to set up sub-word stack arguments for big endian calls. SelectionDAG already knows about this, but fast-isel was ignorant. llvm-svn: 208307
2014-05-08 14:53:50 +02:00
declare void @callee_b0f(i8 %bp10, i8 %bp11, i8 %bp12, i8 %bp13, i8 %bp14, i8 %bp15, i8 %bp17, i8 %bp18, i8 %bp19)
define void @caller_b1f() {
entry:
[FastISel][AArch64] Add MachO large code model support for function calls. Currently the large code model for MachO uses the GOT to make function calls. Emit the required adrp and ldr instructions to load the address from the GOT. Related to <rdar://problem/17733076>. llvm-svn: 214381
2014-07-31 06:10:40 +02:00
; CHECK-BE-LABEL: caller_b1f
; CHECK-BE: strb w{{.*}}, [sp, #7]
[ARM64-BE] Teach fast-isel about how to set up sub-word stack arguments for big endian calls. SelectionDAG already knows about this, but fast-isel was ignorant. llvm-svn: 208307
2014-05-08 14:53:50 +02:00
call void @callee_b0f(i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 42)
ret void
}
[FastISel][AArch64] Add MachO large code model support for function calls. Currently the large code model for MachO uses the GOT to make function calls. Emit the required adrp and ldr instructions to load the address from the GOT. Related to <rdar://problem/17733076>. llvm-svn: 214381
2014-07-31 06:10:40 +02:00
[FastISel][AArch64] Implement the FastLowerArguments hook. This implements basic argument lowering for AArch64 in FastISel. It only handles a small subset of the C calling convention. It supports simple arguments that can be passed in GPR and FPR registers. This should cover most of the trivial cases without falling back to SelectionDAG. This fixes <rdar://problem/17890986>. llvm-svn: 214846
2014-08-05 07:43:48 +02:00
define zeroext i1 @call_arguments1(i1 %a1, i1 %a2, i1 %a3, i1 %a4, i1 %a5, i1 %a6, i1 %a7, i1 %a8) {
; CHECK-LABEL: call_arguments1
; CHECK: and {{w[0-9]+}}, w0, w1
; CHECK-NEXT: and {{w[0-9]+}}, w2, w3
; CHECK-NEXT: and {{w[0-9]+}}, w4, w5
; CHECK-NEXT: and {{w[0-9]+}}, w6, w7
%1 = and i1 %a1, %a2
%2 = and i1 %a3, %a4
%3 = and i1 %a5, %a6
%4 = and i1 %a7, %a8
%5 = and i1 %1, %2
%6 = and i1 %3, %4
%7 = and i1 %5, %6
ret i1 %7
}
define i32 @call_arguments2(i8 zeroext %a1, i8 zeroext %a2, i8 zeroext %a3, i8 zeroext %a4, i8 signext %a5, i8 signext %a6, i8 signext %a7, i8 signext %a8) {
; CHECK-LABEL: call_arguments2
; CHECK: add {{w[0-9]+}}, w0, w1
; CHECK-NEXT: add {{w[0-9]+}}, w2, w3
; CHECK-NEXT: add {{w[0-9]+}}, w4, w5
; CHECK-NEXT: add {{w[0-9]+}}, w6, w7
%a1z = zext i8 %a1 to i32
%a2z = zext i8 %a2 to i32
%a3z = zext i8 %a3 to i32
%a4z = zext i8 %a4 to i32
%a5s = sext i8 %a5 to i32
%a6s = sext i8 %a6 to i32
%a7s = sext i8 %a7 to i32
%a8s = sext i8 %a8 to i32
%1 = add i32 %a1z, %a2z
%2 = add i32 %a3z, %a4z
%3 = add i32 %a5s, %a6s
%4 = add i32 %a7s, %a8s
%5 = add i32 %1, %2
%6 = add i32 %3, %4
%7 = add i32 %5, %6
ret i32 %7
}
define i32 @call_arguments3(i16 zeroext %a1, i16 zeroext %a2, i16 zeroext %a3, i16 zeroext %a4, i16 signext %a5, i16 signext %a6, i16 signext %a7, i16 signext %a8) {
; CHECK-LABEL: call_arguments3
; CHECK: add {{w[0-9]+}}, w0, w1
; CHECK-NEXT: add {{w[0-9]+}}, w2, w3
; CHECK-NEXT: add {{w[0-9]+}}, w4, w5
; CHECK-NEXT: add {{w[0-9]+}}, w6, w7
%a1z = zext i16 %a1 to i32
%a2z = zext i16 %a2 to i32
%a3z = zext i16 %a3 to i32
%a4z = zext i16 %a4 to i32
%a5s = sext i16 %a5 to i32
%a6s = sext i16 %a6 to i32
%a7s = sext i16 %a7 to i32
%a8s = sext i16 %a8 to i32
%1 = add i32 %a1z, %a2z
%2 = add i32 %a3z, %a4z
%3 = add i32 %a5s, %a6s
%4 = add i32 %a7s, %a8s
%5 = add i32 %1, %2
%6 = add i32 %3, %4
%7 = add i32 %5, %6
ret i32 %7
}
define i32 @call_arguments4(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8) {
; CHECK-LABEL: call_arguments4
; CHECK: add {{w[0-9]+}}, w0, w1
; CHECK-NEXT: add {{w[0-9]+}}, w2, w3
; CHECK-NEXT: add {{w[0-9]+}}, w4, w5
; CHECK-NEXT: add {{w[0-9]+}}, w6, w7
%1 = add i32 %a1, %a2
%2 = add i32 %a3, %a4
%3 = add i32 %a5, %a6
%4 = add i32 %a7, %a8
%5 = add i32 %1, %2
%6 = add i32 %3, %4
%7 = add i32 %5, %6
ret i32 %7
}
define i64 @call_arguments5(i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5, i64 %a6, i64 %a7, i64 %a8) {
; CHECK-LABEL: call_arguments5
; CHECK: add {{x[0-9]+}}, x0, x1
; CHECK-NEXT: add {{x[0-9]+}}, x2, x3
; CHECK-NEXT: add {{x[0-9]+}}, x4, x5
; CHECK-NEXT: add {{x[0-9]+}}, x6, x7
%1 = add i64 %a1, %a2
%2 = add i64 %a3, %a4
%3 = add i64 %a5, %a6
%4 = add i64 %a7, %a8
%5 = add i64 %1, %2
%6 = add i64 %3, %4
%7 = add i64 %5, %6
ret i64 %7
}
define float @call_arguments6(float %a1, float %a2, float %a3, float %a4, float %a5, float %a6, float %a7, float %a8) {
; CHECK-LABEL: call_arguments6
; CHECK: fadd {{s[0-9]+}}, s0, s1
; CHECK-NEXT: fadd {{s[0-9]+}}, s2, s3
; CHECK-NEXT: fadd {{s[0-9]+}}, s4, s5
; CHECK-NEXT: fadd {{s[0-9]+}}, s6, s7
%1 = fadd float %a1, %a2
%2 = fadd float %a3, %a4
%3 = fadd float %a5, %a6
%4 = fadd float %a7, %a8
%5 = fadd float %1, %2
%6 = fadd float %3, %4
%7 = fadd float %5, %6
ret float %7
}
define double @call_arguments7(double %a1, double %a2, double %a3, double %a4, double %a5, double %a6, double %a7, double %a8) {
; CHECK-LABEL: call_arguments7
; CHECK: fadd {{d[0-9]+}}, d0, d1
; CHECK-NEXT: fadd {{d[0-9]+}}, d2, d3
; CHECK-NEXT: fadd {{d[0-9]+}}, d4, d5
; CHECK-NEXT: fadd {{d[0-9]+}}, d6, d7
%1 = fadd double %a1, %a2
%2 = fadd double %a3, %a4
%3 = fadd double %a5, %a6
%4 = fadd double %a7, %a8
%5 = fadd double %1, %2
%6 = fadd double %3, %4
%7 = fadd double %5, %6
ret double %7
}
define i64 @call_arguments8(i32 %a1, i64 %a2, i32 %a3, i64 %a4) {
; CHECK-LABEL: call_arguments8
; CHECK: ubfx [[REG1:x[0-9]+]], {{x[0-9]+}}, #0, #32
; CHECK: ubfx [[REG2:x[0-9]+]], {{x[0-9]+}}, #0, #32
; CHECK: add {{x[0-9]+}}, [[REG1]], x1
; CHECK-NEXT: add {{x[0-9]+}}, [[REG2]], x3
%aa1 = zext i32 %a1 to i64
%aa3 = zext i32 %a3 to i64
%1 = add i64 %aa1, %a2
%2 = add i64 %aa3, %a4
%3 = add i64 %1, %2
ret i64 %3
}
define void @call_arguments9(i8 %a1, i16 %a2, i32 %a3, i64 %a4, float %a5, double %a6, i64 %a7, double %a8) {
; CHECK-LABEL: call_arguments9
ret void
}
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