llvm-mirror/test/CodeGen/MIR/AMDGPU/intrinsics.mir

# RUN: llc -mtriple=amdgcn -run-pass none -o - %s | FileCheck %s

--- |

  define void @use_intrin() {
    ret void
  }

...
---
# Completely invalid code, but it checks that intrinsics round-trip properly.
# CHECK: %0(s64) = COPY intrinsic(@llvm.AMDGPU.bfe.i32)
name:            use_intrin
registers:
  - { id: 0, class: _ }
body: |
  bb.0:
    %0(s64) = COPY intrinsic(@llvm.AMDGPU.bfe.i32)
...
CodeGen: add new "intrinsic" MachineOperand kind. This will be used during GlobalISel, where we need a more robust and readable way to write tests than a simple immediate ID. llvm-svn: 277209 2016-07-29 22:32:59 +02:00			`# RUN: llc -mtriple=amdgcn -run-pass none -o - %s \| FileCheck %s`

			`--- \|`

			`define void @use_intrin() {`
			`ret void`
			`}`

			`...`
			`---`
			`# Completely invalid code, but it checks that intrinsics round-trip properly.`
GlobalISel: move type information to MachineRegisterInfo. We want each register to have a canonical type, which means the best place to store this is in MachineRegisterInfo rather than on every MachineInstr that happens to use or define that register. Most changes following from this are pretty simple (you need an MRI anyway if you're going to be doing any transformations, so just check the type there). But legalization doesn't really want to check redundant operands (when, for example, a G_ADD only ever has one type) so I've made use of MCInstrDesc's operand type field to encode these constraints and limit legalization's work. As an added bonus, more validation is possible, both in MachineVerifier and MachineIRBuilder (coming soon). llvm-svn: 281035 2016-09-09 13:46:34 +02:00			`# CHECK: %0(s64) = COPY intrinsic(@llvm.AMDGPU.bfe.i32)`
CodeGen: add new "intrinsic" MachineOperand kind. This will be used during GlobalISel, where we need a more robust and readable way to write tests than a simple immediate ID. llvm-svn: 277209 2016-07-29 22:32:59 +02:00			`name: use_intrin`
			`registers:`
			`- { id: 0, class: _ }`
			`body: \|`
			`bb.0:`
GlobalISel: move type information to MachineRegisterInfo. We want each register to have a canonical type, which means the best place to store this is in MachineRegisterInfo rather than on every MachineInstr that happens to use or define that register. Most changes following from this are pretty simple (you need an MRI anyway if you're going to be doing any transformations, so just check the type there). But legalization doesn't really want to check redundant operands (when, for example, a G_ADD only ever has one type) so I've made use of MCInstrDesc's operand type field to encode these constraints and limit legalization's work. As an added bonus, more validation is possible, both in MachineVerifier and MachineIRBuilder (coming soon). llvm-svn: 281035 2016-09-09 13:46:34 +02:00			`%0(s64) = COPY intrinsic(@llvm.AMDGPU.bfe.i32)`
CodeGen: add new "intrinsic" MachineOperand kind. This will be used during GlobalISel, where we need a more robust and readable way to write tests than a simple immediate ID. llvm-svn: 277209 2016-07-29 22:32:59 +02:00			`...`