2004-06-01 08:48:00 +02:00
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN"
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"http://www.w3.org/TR/html4/strict.dtd">
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<html>
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<head>
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<title>The LLVM Target-Independent Code Generator</title>
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<link rel="stylesheet" href="llvm.css" type="text/css">
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</head>
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<body>
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<div class="doc_title">
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The LLVM Target-Independent Code Generator
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</div>
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<ol>
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<li><a href="#introduction">Introduction</a>
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<ul>
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<li><a href="#required">Required components in the code generator</a></li>
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<li><a href="#high-level-design">The high-level design of the code generator</a></li>
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<li><a href="#tablegen">Using TableGen for target description</a></li>
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</ul>
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</li>
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<li><a href="#targetdesc">Target description classes</a>
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<ul>
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<li><a href="#targetmachine">The <tt>TargetMachine</tt> class</a></li>
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<li><a href="#targetdata">The <tt>TargetData</tt> class</a></li>
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<li><a href="#mregisterinfo">The <tt>MRegisterInfo</tt> class</a></li>
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<li><a href="#targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a></li>
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<li><a href="#targetframeinfo">The <tt>TargetFrameInfo</tt> class</a></li>
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<li><a href="#targetjitinfo">The <tt>TargetJITInfo</tt> class</a></li>
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</ul>
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</li>
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<li><a href="#codegendesc">Machine code description classes</a>
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</li>
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<li><a href="#codegenalgs">Target-independent code generation algorithms</a>
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</li>
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<li><a href="#targetimpls">Target description implementations</a>
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<ul>
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<li><a href="#x86">The X86 backend</a></li>
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</ul>
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</li>
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</ol>
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<div class="doc_author">
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<p>Written by <a href="mailto:sabre@nondot.org">Chris Lattner</a></p>
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</div>
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2004-06-01 19:18:11 +02:00
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<div class="doc_warning">
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<p>Warning: This is a work in progress.</p>
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</div>
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2004-06-01 08:48:00 +02:00
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<!-- *********************************************************************** -->
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<div class="doc_section">
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<a name="introduction">Introduction</a>
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</div>
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<!-- *********************************************************************** -->
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<div class="doc_text">
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<p>The LLVM target-independent code generator is a framework that provides a
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suite of reusable components for translating the LLVM internal representation to
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the machine code for a specified target -- either in assembly form (suitable for
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a static compiler) or in binary machine code format (usable for a JIT compiler).
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The LLVM target-independent code generator consists of four main components:</p>
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<ol>
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<li><a href="#targetdesc">Abstract target description</a> interfaces which
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capture improtant properties about various aspects of the machine independently
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of how they will be used. These interfaces are defined in
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<tt>include/llvm/Target/</tt>.</li>
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<li>Classes used to represent the <a href="#codegendesc">machine code</a> being
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generator for a target. These classes are intended to be abstract enough to
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represent the machine code for <i>any</i> target machine. These classes are
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defined in <tt>include/llvm/CodeGen/</tt>.</li>
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<li><a href="#codegenalgs">Target-independent algorithms</a> used to implement
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various phases of native code generation (register allocation, scheduling, stack
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frame representation, etc). This code lives in <tt>lib/CodeGen/</tt>.</li>
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<li><a href="#targetimpls">Implementations of the abstract target description
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interfaces</a> for particular targets. These machine descriptions make use of
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the components provided by LLVM, and can optionally provide custom
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target-specific passes, to build complete code generators for a specific target.
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Target descriptions live in <tt>lib/Target/</tt>.</li>
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</ol>
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<p>
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Depending on which part of the code generator you are interested in working on,
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different pieces of this will be useful to you. In any case, you should be
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familiar with the <a href="#targetdesc">target description</a> and <a
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href="#codegendesc">machine code representation</a> classes. If you want to add
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a backend for a new target, you will need <a href="#targetimpls">implement the
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targe description</a> classes for your new target and understand the <a
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href="LangRef.html">LLVM code representation</a>. If you are interested in
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implementing a new <a href="#codegenalgs">code generation algorithm</a>, it
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should only depend on the target-description and machine code representation
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classes, ensuring that it is portable.
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</p>
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</div>
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<!-- ======================================================================= -->
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<div class="doc_subsection">
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<a name="required">Required components in the code generator</a>
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</div>
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<div class="doc_text">
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<p>The two pieces of the LLVM code generator are the high-level interface to the
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code generator and the set of reusable components that can be used to build
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target-specific backends. The two most important interfaces (<a
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href="#targetmachine"><tt>TargetMachine</tt></a> and <a
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href="#targetdata"><tt>TargetData</tt></a> classes) are the only ones that are
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required to be defined for a backend to fit into the LLVM system, but the others
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must be defined if the reusable code generator components are going to be
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used.</p>
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<p>This design has two important implications. The first is that LLVM can
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support completely non-traditional code generation targets. For example, the C
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backend does not require register allocation, instruction selection, or any of
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the other standard components provided by the system. As such, it only
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implements these two interfaces, and does its own thing. Another example of a
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code generator like this is a (purely hypothetical) backend that converts LLVM
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to the GCC RTL form and uses GCC to emit machine code for a target.</p>
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<p>The other implication of this design is that it is possible to design and
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implement radically different code generators in the LLVM system that do not
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make use of any of the built-in components. Doing so is not recommended at all,
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but could be required for radically different targets that do not fit into the
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LLVM machine description model: programmable FPGAs for example.</p>
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2004-06-02 09:06:06 +02:00
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<p><b>Important Note:</b> For historical reasons, the LLVM SparcV9 code
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generator uses almost entirely different code paths than described in this
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document. For this reason, there are some deprecated interfaces (such as
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<tt>TargetRegInfo</tt> and <tt>TargetSchedInfo</tt>), which are only used by the
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V9 backend and should not be used by any other targets. Also, all code in the
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<tt>lib/Target/SparcV9</tt> directory and subdirectories should be considered
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deprecated, and should not be used as the basis for future code generator work.
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The SparcV9 backend is slowly being merged into the rest of the target
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independent code generators, but this is a low-priority process with no
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predictable completion date.</p>
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2004-06-01 08:48:00 +02:00
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</div>
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<!-- ======================================================================= -->
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<div class="doc_subsection">
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<a name="high-level-design">The high-level design of the code generator</a>
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</div>
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<div class="doc_text">
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<p>The LLVM target-indendent code generator is designed to support efficient and
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quality code generation for standard register-based microprocessors. Code
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generation in this model is divided into the following stages:</p>
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<ol>
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<li><b>Instruction Selection</b> - Determining a efficient implementation of the
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input LLVM code in the target instruction set. This stage produces the initial
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code for the program in the target instruction set the makes use of virtual
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registers in SSA form and physical registers that represent any required
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register assignments due to target constraints or calling conventions.</li>
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<li><b>SSA-based Machine Code Optimizations</b> - This (optional) stage consists
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of a series of machine-code optimizations that operate on the SSA-form produced
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by the instruction selector. Optimizations like modulo-scheduling, normal
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scheduling, or peephole optimization work here.</li>
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<li><b>Register Allocation</b> - The target code is transformed from an infinite
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virtual register file in SSA form to the concrete register file used by the
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target. This phase introduces spill code and eliminates all virtual register
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references from the program.</li>
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<li><b>Prolog/Epilog Code Insertion</b> - Once the machine code has been
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generated for the function and the amount of stack space required is known (used
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for LLVM alloca's and spill slots), the prolog and epilog code for the function
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can be inserted and "abstract stack location references" can be eliminated.
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This stage is responsible for implementing optimizations like frame-pointer
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elimination and stack packing.</li>
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<li><b>Late Machine Code Optimizations</b> - Optimizations that operate on
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"final" machine code can go here, such as spill code scheduling and peephole
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optimizations.</li>
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<li><b>Code Emission</b> - The final stage actually outputs the machine code for
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the current function, either in the target assembler format or in machine
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code.</li>
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</ol>
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<p>
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The code generator is based on the assumption that the instruction selector will
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use an optimal pattern matching selector to create high-quality sequences of
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native code. Alternative code generator designs based on pattern expansion and
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aggressive iterative peephole optimization are much slower. This design is
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designed to permit efficient compilation (important for JIT environments) and
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aggressive optimization (used when generate code offline) by allowing components
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of varying levels of sophisication to be used for any step of compilation.</p>
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<p>
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In addition to these stages, target implementations can insert arbitrary
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target-specific passes into the flow. For example, the X86 target uses a
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special pass to handle the 80x87 floating point stack architecture. Other
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targets with unusual requirements can be supported with custom passes as needed.
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</p>
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</div>
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<!-- ======================================================================= -->
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<div class="doc_subsection">
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<a name="tablegen">Using TableGen for target description</a>
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</div>
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<div class="doc_text">
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2004-06-01 20:35:00 +02:00
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<p>The target description classes require a detailed description of the target
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architecture. These target descriptions often have a large amount of common
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information (e.g., an add instruction is almost identical to a sub instruction).
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In order to allow the maximum amount of commonality to be factored out, the LLVM
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code generator uses the <a href="TableGenFundamentals.html">TableGen</a> tool to
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describe big chunks of the target machine, which allows the use of domain- and
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target-specific abstractions to reduce the amount of repetition.
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</p>
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</div>
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<!-- *********************************************************************** -->
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<div class="doc_section">
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<a name="targetdesc">Target description classes</a>
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</div>
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<!-- *********************************************************************** -->
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<div class="doc_text">
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<p>The LLVM target description classes (which are located in the
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<tt>include/llvm/Target</tt> directory) provide an abstract description of the
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target machine, independent of any particular client. These classes are
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designed to capture the <i>abstract</i> properties of the target (such as what
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instruction and registers it has), and do not incorporate any particular pieces
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of code generation algorithms (these interfaces do not take interference graphs
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as inputs or other algorithm-specific data structures).</p>
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<p>All of the target description classes (except the <tt><a
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href="#targetdata">TargetData</a></tt> class) are designed to be subclassed by
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the concrete target implementation, and have virtual methods implemented. To
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get to these implementations, <tt><a
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href="#targetmachine">TargetMachine</a></tt> class provides accessors that
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should be implemented by the target.</p>
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</div>
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<!-- ======================================================================= -->
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<div class="doc_subsection">
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<a name="targetmachine">The <tt>TargetMachine</tt> class</a>
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</div>
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<div class="doc_text">
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<p>The <tt>TargetMachine</tt> class provides virtual methods that are used to
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access the target-specific implementations of the various target description
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classes (with the <tt>getInstrInfo</tt>, <tt>getRegisterInfo</tt>,
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<tt>getFrameInfo</tt>, ... methods). This class is designed to be subclassed by
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a concrete target implementation (e.g., <tt>X86TargetMachine</tt>) which
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implements the various virtual methods. The only required target description
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class is the <a href="#targetdata"><tt>TargetData</tt></a> class, but if the
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code generator components are to be used, the other interfaces should be
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implemented as well.</p>
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</div>
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<!-- ======================================================================= -->
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<div class="doc_subsection">
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<a name="targetdata">The <tt>TargetData</tt> class</a>
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</div>
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<div class="doc_text">
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<p>The <tt>TargetData</tt> class is the only required target description class,
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and it is the only class that is not extensible (it cannot be derived from). It
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specifies information about how the target lays out memory for structures, the
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alignment requirements for various data types, the size of pointers in the
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target, and whether the target is little- or big-endian.</p>
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</div>
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<!-- ======================================================================= -->
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<div class="doc_subsection">
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<a name="mregisterinfo">The <tt>MRegisterInfo</tt> class</a>
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</div>
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<div class="doc_text">
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<p>The <tt>MRegisterInfo</tt> class (which will eventually be renamed to
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<tt>TargetRegisterInfo</tt>) is used to describe the register file of the
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target and any interactions between the registers.</p>
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<p>Registers in the code generator are represented in the code generator by
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unsigned numbers. Physical registers (those that actually exist in the target
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description) are unique small numbers, and virtual registers are generally
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large.</p>
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<p>Each register in the processor description has an associated
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<tt>MRegisterDesc</tt> entry, which provides a textual name for the register
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(used for assembly output and debugging dumps), a set of aliases (used to
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indicate that one register overlaps with another), and some flag bits.
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</p>
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<p>In addition to the per-register description, the <tt>MRegisterInfo</tt> class
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exposes a set of processor specific register classes (instances of the
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<tt>TargetRegisterClass</tt> class). Each register class contains sets of
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registers that have the same properties (for example, they are all 32-bit
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integer registers). Each SSA virtual register created by the instruction
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selector has an associated register class. When the register allocator runs, it
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replaces virtual registers with a physical register in the set.</p>
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<p>
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The target-specific implementations of these classes is auto-generated from a <a
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href="TableGenFundamentals.html">TableGen</a> description of the register file.
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</p>
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</div>
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<!-- ======================================================================= -->
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<div class="doc_subsection">
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2004-06-01 19:18:11 +02:00
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<a name="targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a>
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2004-06-01 08:48:00 +02:00
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</div>
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<!-- ======================================================================= -->
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<div class="doc_subsection">
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2004-06-01 19:18:11 +02:00
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<a name="targetframeinfo">The <tt>TargetFrameInfo</tt> class</a>
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2004-06-01 08:48:00 +02:00
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</div>
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<!-- ======================================================================= -->
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<div class="doc_subsection">
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2004-06-01 19:18:11 +02:00
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<a name="targetjitinfo">The <tt>TargetJITInfo</tt> class</a>
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2004-06-01 08:48:00 +02:00
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</div>
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<!-- *********************************************************************** -->
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<div class="doc_section">
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<a name="codegendesc">Machine code description classes</a>
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</div>
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<!-- *********************************************************************** -->
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<!-- *********************************************************************** -->
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<hr>
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<address>
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<a href="mailto:sabre@nondot.org">Chris Lattner</a><br>
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<a href="http://llvm.cs.uiuc.edu">The LLVM Compiler Infrastructure</a><br>
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Last modified: $Date$
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</address>
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