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llvm-mirror/test/CodeGen/Thumb2/mve-vpt-nots.mir

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[ARM] Masked load and store and predicate tests. NFC llvm-svn: 370325
2019-08-29 10:32:12 +00:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
[ARM] Change all tests from "thumbv8.1-m.main" to "thumbv8.1m.main". NFC
2020-03-04 12:56:42 +00:00
# RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve -run-pass arm-mve-vpt %s -o - | FileCheck %s
[ARM] Masked load and store and predicate tests. NFC llvm-svn: 370325
2019-08-29 10:32:12 +00:00
--- |
define arm_aapcs_vfpcc <4 x i32> @vpnot(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
entry:
%0 = icmp slt <4 x i32> %a, zeroinitializer
%c2 = icmp sgt <4 x i32> %b, zeroinitializer
%c3 = icmp eq <4 x i32> %c, zeroinitializer
%o1 = and <4 x i1> %0, %c2
%o2 = xor <4 x i1> %o1, <i1 true, i1 true, i1 true, i1 true>
%o = and <4 x i1> %c3, %o2
%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
ret <4 x i32> %s
}
define arm_aapcs_vfpcc <4 x i32> @vpnot_end(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
entry:
%0 = icmp slt <4 x i32> %a, zeroinitializer
%c2 = icmp sgt <4 x i32> %b, zeroinitializer
%c3 = icmp eq <4 x i32> %c, zeroinitializer
%o1 = and <4 x i1> %0, %c2
%o2 = xor <4 x i1> %o1, <i1 true, i1 true, i1 true, i1 true>
br label %bb2
bb2:
%o = and <4 x i1> %c3, %o2
%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
ret <4 x i32> %s
}
define arm_aapcs_vfpcc <4 x i32> @vpnot_two(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
entry:
unreachable
}
define arm_aapcs_vfpcc <4 x i32> @vpnot_lots(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
entry:
unreachable
}
define arm_aapcs_vfpcc <4 x i32> @vpnot_first(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
entry:
unreachable
}
define arm_aapcs_vfpcc <4 x i32> @vpnot_many(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
entry:
unreachable
}
...
---
name: vpnot
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
2019-09-11 11:16:48 +00:00
alignment: 4
[ARM] Masked load and store and predicate tests. NFC llvm-svn: 370325
2019-08-29 10:32:12 +00:00
tracksRegLiveness: true
liveins:
- { reg: '$q0', virtual-reg: '' }
- { reg: '$q1', virtual-reg: '' }
- { reg: '$q2', virtual-reg: '' }
body: |
bb.0.entry:
liveins: $q0, $q1, $q2
; CHECK-LABEL: name: vpnot
; CHECK: liveins: $q0, $q1, $q2
[Target][ARM] Improvements to the VPT Block Insertion Pass This allows the MVE VPT Block insertion pass to remove VPNOTs in order to create more complex VPT blocks such as TE, TEET, TETE, etc. Differential Revision: https://reviews.llvm.org/D75993
2020-03-09 16:40:33 +00:00
; CHECK: BUNDLE implicit-def $vpr, implicit $q0, implicit $zr, implicit $q1, implicit killed $q2 {
; CHECK: MVE_VPTv4s32r 12, renamable $q0, $zr, 11, implicit-def $vpr
[ARM] Fold VCMP into VPT MVE has VPT instructions, which perform the duties of both a VCMP and a VPST in a single instruction, performing the compare and starting the VPT block in one. This teaches the MVEVPTBlockPass to fold them, searching back through the basicblock for a valid VCMP and creating the VPT from its operands. There are some changes to the VPT instructions to accommodate this, altering the order of the operands to match the VCMP better, and changing P0 register defs to be VPR defs, as is used in other places. Differential Revision: https://reviews.llvm.org/D66577 llvm-svn: 371982
2019-09-16 13:02:41 +00:00
; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, internal killed renamable $vpr
[Target][ARM] Improvements to the VPT Block Insertion Pass This allows the MVE VPT Block insertion pass to remove VPNOTs in order to create more complex VPT blocks such as TE, TEET, TETE, etc. Differential Revision: https://reviews.llvm.org/D75993
2020-03-09 16:40:33 +00:00
; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 2, internal killed renamable $vpr
[ARM] Masked load and store and predicate tests. NFC llvm-svn: 370325
2019-08-29 10:32:12 +00:00
; CHECK: }
[ARM] Fixup the creation of VPT blocks This attempts to just fix the creation of VPT blocks, fixing up the iterating, which instructions are considered in the bundle, and making sure that we do not overrun the end of the block. Differential Revision: https://reviews.llvm.org/D67219 llvm-svn: 371064
2019-09-05 13:37:04 +00:00
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr
[MIR][ARM] MachineOperand comments This adds infrastructure to print and parse MIR MachineOperand comments. The motivation for the ARM backend is to print condition code names instead of magic constants that are difficult to read (for human beings). For example, instead of this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg t2Bcc %bb.4, 0, killed $cpsr we now print this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr This shows that MachineOperand comments are enclosed between /* and */. In this example, the EOR instruction is not conditionally executed (i.e. it is "always executed"), which is encoded by the 14 immediate machine operand. Thus, now this machine operand has /* CC::always */ as a comment. The 0 on the next conditional branch instruction represents the equal condition code, thus now this operand has /* CC:eq */ as a comment. As it is a comment, the MI lexer/parser completely ignores it. The benefit is that this keeps the change in the lexer extremely minimal and no target specific parsing needs to be done. The changes on the MIPrinter side are also minimal, as there is only one target hooks that is used to create the machine operand comments. Differential Revision: https://reviews.llvm.org/D74306
2020-02-24 14:19:21 +00:00
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
[ARM] Masked load and store and predicate tests. NFC llvm-svn: 370325
2019-08-29 10:32:12 +00:00
renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg
renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr
renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr
tBX_RET 14, $noreg, implicit $q0
...
---
name: vpnot_end
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
2019-09-11 11:16:48 +00:00
alignment: 4
[ARM] Masked load and store and predicate tests. NFC llvm-svn: 370325
2019-08-29 10:32:12 +00:00
tracksRegLiveness: true
liveins:
- { reg: '$q0', virtual-reg: '' }
- { reg: '$q1', virtual-reg: '' }
- { reg: '$q2', virtual-reg: '' }
body: |
; CHECK-LABEL: name: vpnot_end
; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $q0, $q1, $q2
[ARM] Fold VCMP into VPT MVE has VPT instructions, which perform the duties of both a VCMP and a VPST in a single instruction, performing the compare and starting the VPT block in one. This teaches the MVEVPTBlockPass to fold them, searching back through the basicblock for a valid VCMP and creating the VPT from its operands. There are some changes to the VPT instructions to accommodate this, altering the order of the operands to match the VCMP better, and changing P0 register defs to be VPR defs, as is used in other places. Differential Revision: https://reviews.llvm.org/D66577 llvm-svn: 371982
2019-09-16 13:02:41 +00:00
; CHECK: BUNDLE implicit-def $vpr, implicit $q0, implicit $zr, implicit $q1 {
; CHECK: MVE_VPTv4s32r 8, renamable $q0, $zr, 11, implicit-def $vpr
; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, internal killed renamable $vpr
[ARM] Masked load and store and predicate tests. NFC llvm-svn: 370325
2019-08-29 10:32:12 +00:00
; CHECK: }
[ARM] Fixup the creation of VPT blocks This attempts to just fix the creation of VPT blocks, fixing up the iterating, which instructions are considered in the bundle, and making sure that we do not overrun the end of the block. Differential Revision: https://reviews.llvm.org/D67219 llvm-svn: 371064
2019-09-05 13:37:04 +00:00
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
[ARM] Masked load and store and predicate tests. NFC llvm-svn: 370325
2019-08-29 10:32:12 +00:00
; CHECK: bb.1.bb2:
; CHECK: liveins: $q0, $q1, $q2, $vpr
[ARM][MVE] Change VPST to use, not def, VPR Unlike VPT, VPST just uses the current value of VPR.P0. Differential Revision: https://reviews.llvm.org/D69037 llvm-svn: 375087
2019-10-17 08:46:31 +00:00
; CHECK: BUNDLE implicit-def $vpr, implicit killed $vpr, implicit killed $q2, implicit $zr {
; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr
[ARM] Masked load and store and predicate tests. NFC llvm-svn: 370325
2019-08-29 10:32:12 +00:00
; CHECK: }
[ARM] Fixup the creation of VPT blocks This attempts to just fix the creation of VPT blocks, fixing up the iterating, which instructions are considered in the bundle, and making sure that we do not overrun the end of the block. Differential Revision: https://reviews.llvm.org/D67219 llvm-svn: 371064
2019-09-05 13:37:04 +00:00
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr
[MIR][ARM] MachineOperand comments This adds infrastructure to print and parse MIR MachineOperand comments. The motivation for the ARM backend is to print condition code names instead of magic constants that are difficult to read (for human beings). For example, instead of this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg t2Bcc %bb.4, 0, killed $cpsr we now print this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr This shows that MachineOperand comments are enclosed between /* and */. In this example, the EOR instruction is not conditionally executed (i.e. it is "always executed"), which is encoded by the 14 immediate machine operand. Thus, now this machine operand has /* CC::always */ as a comment. The 0 on the next conditional branch instruction represents the equal condition code, thus now this operand has /* CC:eq */ as a comment. As it is a comment, the MI lexer/parser completely ignores it. The benefit is that this keeps the change in the lexer extremely minimal and no target specific parsing needs to be done. The changes on the MIPrinter side are also minimal, as there is only one target hooks that is used to create the machine operand comments. Differential Revision: https://reviews.llvm.org/D74306
2020-02-24 14:19:21 +00:00
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
[ARM] Masked load and store and predicate tests. NFC llvm-svn: 370325
2019-08-29 10:32:12 +00:00
bb.0.entry:
liveins: $q0, $q1, $q2
renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg
renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
bb.1.bb2:
liveins: $q0, $q1, $q2, $vpr
renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr
renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr
tBX_RET 14, $noreg, implicit $q0
...
---
name: vpnot_two
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
2019-09-11 11:16:48 +00:00
alignment: 4
[ARM] Masked load and store and predicate tests. NFC llvm-svn: 370325
2019-08-29 10:32:12 +00:00
tracksRegLiveness: true
liveins:
- { reg: '$q0', virtual-reg: '' }
- { reg: '$q1', virtual-reg: '' }
- { reg: '$q2', virtual-reg: '' }
body: |
bb.0.entry:
liveins: $q0, $q1, $q2
; CHECK-LABEL: name: vpnot_two
; CHECK: liveins: $q0, $q1, $q2
[ARM] Fold VCMP into VPT MVE has VPT instructions, which perform the duties of both a VCMP and a VPST in a single instruction, performing the compare and starting the VPT block in one. This teaches the MVEVPTBlockPass to fold them, searching back through the basicblock for a valid VCMP and creating the VPT from its operands. There are some changes to the VPT instructions to accommodate this, altering the order of the operands to match the VCMP better, and changing P0 register defs to be VPR defs, as is used in other places. Differential Revision: https://reviews.llvm.org/D66577 llvm-svn: 371982
2019-09-16 13:02:41 +00:00
; CHECK: BUNDLE implicit-def $vpr, implicit $q0, implicit $zr, implicit $q1 {
; CHECK: MVE_VPTv4s32r 8, renamable $q0, $zr, 11, implicit-def $vpr
; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, internal killed renamable $vpr
[ARM] Masked load and store and predicate tests. NFC llvm-svn: 370325
2019-08-29 10:32:12 +00:00
; CHECK: }
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
[ARM] Fixup the creation of VPT blocks This attempts to just fix the creation of VPT blocks, fixing up the iterating, which instructions are considered in the bundle, and making sure that we do not overrun the end of the block. Differential Revision: https://reviews.llvm.org/D67219 llvm-svn: 371064
2019-09-05 13:37:04 +00:00
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
[ARM][MVE] Change VPST to use, not def, VPR Unlike VPT, VPST just uses the current value of VPR.P0. Differential Revision: https://reviews.llvm.org/D69037 llvm-svn: 375087
2019-10-17 08:46:31 +00:00
; CHECK: BUNDLE implicit-def $vpr, implicit killed $vpr, implicit killed $q2, implicit $zr {
; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr
[ARM] Masked load and store and predicate tests. NFC llvm-svn: 370325
2019-08-29 10:32:12 +00:00
; CHECK: }
[ARM] Fixup the creation of VPT blocks This attempts to just fix the creation of VPT blocks, fixing up the iterating, which instructions are considered in the bundle, and making sure that we do not overrun the end of the block. Differential Revision: https://reviews.llvm.org/D67219 llvm-svn: 371064
2019-09-05 13:37:04 +00:00
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr
[MIR][ARM] MachineOperand comments This adds infrastructure to print and parse MIR MachineOperand comments. The motivation for the ARM backend is to print condition code names instead of magic constants that are difficult to read (for human beings). For example, instead of this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg t2Bcc %bb.4, 0, killed $cpsr we now print this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr This shows that MachineOperand comments are enclosed between /* and */. In this example, the EOR instruction is not conditionally executed (i.e. it is "always executed"), which is encoded by the 14 immediate machine operand. Thus, now this machine operand has /* CC::always */ as a comment. The 0 on the next conditional branch instruction represents the equal condition code, thus now this operand has /* CC:eq */ as a comment. As it is a comment, the MI lexer/parser completely ignores it. The benefit is that this keeps the change in the lexer extremely minimal and no target specific parsing needs to be done. The changes on the MIPrinter side are also minimal, as there is only one target hooks that is used to create the machine operand comments. Differential Revision: https://reviews.llvm.org/D74306
2020-02-24 14:19:21 +00:00
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
[ARM] Masked load and store and predicate tests. NFC llvm-svn: 370325
2019-08-29 10:32:12 +00:00
renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg
renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr
renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr
tBX_RET 14, $noreg, implicit $q0
...
---
name: vpnot_lots
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
2019-09-11 11:16:48 +00:00
alignment: 4
[ARM] Masked load and store and predicate tests. NFC llvm-svn: 370325
2019-08-29 10:32:12 +00:00
tracksRegLiveness: true
liveins:
- { reg: '$q0', virtual-reg: '' }
- { reg: '$q1', virtual-reg: '' }
- { reg: '$q2', virtual-reg: '' }
body: |
bb.0.entry:
liveins: $q0, $q1, $q2
; CHECK-LABEL: name: vpnot_lots
; CHECK: liveins: $q0, $q1, $q2
[ARM] Fold VCMP into VPT MVE has VPT instructions, which perform the duties of both a VCMP and a VPST in a single instruction, performing the compare and starting the VPT block in one. This teaches the MVEVPTBlockPass to fold them, searching back through the basicblock for a valid VCMP and creating the VPT from its operands. There are some changes to the VPT instructions to accommodate this, altering the order of the operands to match the VCMP better, and changing P0 register defs to be VPR defs, as is used in other places. Differential Revision: https://reviews.llvm.org/D66577 llvm-svn: 371982
2019-09-16 13:02:41 +00:00
; CHECK: BUNDLE implicit-def $vpr, implicit $q0, implicit $zr, implicit $q1 {
; CHECK: MVE_VPTv4s32r 8, renamable $q0, $zr, 11, implicit-def $vpr
; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, internal killed renamable $vpr
[ARM] Masked load and store and predicate tests. NFC llvm-svn: 370325
2019-08-29 10:32:12 +00:00
; CHECK: }
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
[ARM] Fixup the creation of VPT blocks This attempts to just fix the creation of VPT blocks, fixing up the iterating, which instructions are considered in the bundle, and making sure that we do not overrun the end of the block. Differential Revision: https://reviews.llvm.org/D67219 llvm-svn: 371064
2019-09-05 13:37:04 +00:00
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
[ARM][MVE] Change VPST to use, not def, VPR Unlike VPT, VPST just uses the current value of VPR.P0. Differential Revision: https://reviews.llvm.org/D69037 llvm-svn: 375087
2019-10-17 08:46:31 +00:00
; CHECK: BUNDLE implicit-def $vpr, implicit killed $vpr, implicit killed $q2, implicit $zr {
; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr
[ARM] Masked load and store and predicate tests. NFC llvm-svn: 370325
2019-08-29 10:32:12 +00:00
; CHECK: }
[ARM] Fixup the creation of VPT blocks This attempts to just fix the creation of VPT blocks, fixing up the iterating, which instructions are considered in the bundle, and making sure that we do not overrun the end of the block. Differential Revision: https://reviews.llvm.org/D67219 llvm-svn: 371064
2019-09-05 13:37:04 +00:00
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr
[MIR][ARM] MachineOperand comments This adds infrastructure to print and parse MIR MachineOperand comments. The motivation for the ARM backend is to print condition code names instead of magic constants that are difficult to read (for human beings). For example, instead of this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg t2Bcc %bb.4, 0, killed $cpsr we now print this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr This shows that MachineOperand comments are enclosed between /* and */. In this example, the EOR instruction is not conditionally executed (i.e. it is "always executed"), which is encoded by the 14 immediate machine operand. Thus, now this machine operand has /* CC::always */ as a comment. The 0 on the next conditional branch instruction represents the equal condition code, thus now this operand has /* CC:eq */ as a comment. As it is a comment, the MI lexer/parser completely ignores it. The benefit is that this keeps the change in the lexer extremely minimal and no target specific parsing needs to be done. The changes on the MIPrinter side are also minimal, as there is only one target hooks that is used to create the machine operand comments. Differential Revision: https://reviews.llvm.org/D74306
2020-02-24 14:19:21 +00:00
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
[ARM] Masked load and store and predicate tests. NFC llvm-svn: 370325
2019-08-29 10:32:12 +00:00
renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg
renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr
renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr
tBX_RET 14, $noreg, implicit $q0
...
---
name: vpnot_first
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
2019-09-11 11:16:48 +00:00
alignment: 4
[ARM] Masked load and store and predicate tests. NFC llvm-svn: 370325
2019-08-29 10:32:12 +00:00
tracksRegLiveness: true
liveins:
- { reg: '$q0', virtual-reg: '' }
- { reg: '$q1', virtual-reg: '' }
- { reg: '$q2', virtual-reg: '' }
body: |
bb.0.entry:
liveins: $q0, $q1, $q2
; CHECK-LABEL: name: vpnot_first
; CHECK: liveins: $q0, $q1, $q2
; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
[ARM][MVE] Change VPST to use, not def, VPR Unlike VPT, VPST just uses the current value of VPR.P0. Differential Revision: https://reviews.llvm.org/D69037 llvm-svn: 375087
2019-10-17 08:46:31 +00:00
; CHECK: BUNDLE implicit-def $vpr, implicit killed $vpr, implicit $q1, implicit $zr, implicit killed $q2 {
; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr
[ARM] Masked load and store and predicate tests. NFC llvm-svn: 370325
2019-08-29 10:32:12 +00:00
; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, internal killed renamable $vpr
; CHECK: }
[ARM] Fixup the creation of VPT blocks This attempts to just fix the creation of VPT blocks, fixing up the iterating, which instructions are considered in the bundle, and making sure that we do not overrun the end of the block. Differential Revision: https://reviews.llvm.org/D67219 llvm-svn: 371064
2019-09-05 13:37:04 +00:00
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr
[MIR][ARM] MachineOperand comments This adds infrastructure to print and parse MIR MachineOperand comments. The motivation for the ARM backend is to print condition code names instead of magic constants that are difficult to read (for human beings). For example, instead of this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg t2Bcc %bb.4, 0, killed $cpsr we now print this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr This shows that MachineOperand comments are enclosed between /* and */. In this example, the EOR instruction is not conditionally executed (i.e. it is "always executed"), which is encoded by the 14 immediate machine operand. Thus, now this machine operand has /* CC::always */ as a comment. The 0 on the next conditional branch instruction represents the equal condition code, thus now this operand has /* CC:eq */ as a comment. As it is a comment, the MI lexer/parser completely ignores it. The benefit is that this keeps the change in the lexer extremely minimal and no target specific parsing needs to be done. The changes on the MIPrinter side are also minimal, as there is only one target hooks that is used to create the machine operand comments. Differential Revision: https://reviews.llvm.org/D74306
2020-02-24 14:19:21 +00:00
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
[ARM] Masked load and store and predicate tests. NFC llvm-svn: 370325
2019-08-29 10:32:12 +00:00
renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr
renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr
renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr
tBX_RET 14, $noreg, implicit $q0
...
---
name: vpnot_many
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
2019-09-11 11:16:48 +00:00
alignment: 4
[ARM] Masked load and store and predicate tests. NFC llvm-svn: 370325
2019-08-29 10:32:12 +00:00
tracksRegLiveness: true
liveins:
- { reg: '$q0', virtual-reg: '' }
- { reg: '$q1', virtual-reg: '' }
- { reg: '$q2', virtual-reg: '' }
body: |
bb.0.entry:
liveins: $q0, $q1, $q2
; CHECK-LABEL: name: vpnot_many
; CHECK: liveins: $q0, $q1, $q2
; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
[Target][ARM] Improvements to the VPT Block Insertion Pass This allows the MVE VPT Block insertion pass to remove VPNOTs in order to create more complex VPT blocks such as TE, TEET, TETE, etc. Differential Revision: https://reviews.llvm.org/D75993
2020-03-09 16:40:33 +00:00
; CHECK: BUNDLE implicit-def $vpr, implicit killed $vpr, implicit $q1, implicit $zr, implicit killed $q2 {
; CHECK: MVE_VPST 12, implicit $vpr
[ARM][MVE] Change VPST to use, not def, VPR Unlike VPT, VPST just uses the current value of VPR.P0. Differential Revision: https://reviews.llvm.org/D69037 llvm-svn: 375087
2019-10-17 08:46:31 +00:00
; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr
[Target][ARM] Improvements to the VPT Block Insertion Pass This allows the MVE VPT Block insertion pass to remove VPNOTs in order to create more complex VPT blocks such as TE, TEET, TETE, etc. Differential Revision: https://reviews.llvm.org/D75993
2020-03-09 16:40:33 +00:00
; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 2, internal killed renamable $vpr
[ARM] Masked load and store and predicate tests. NFC llvm-svn: 370325
2019-08-29 10:32:12 +00:00
; CHECK: }
[ARM] Fixup the creation of VPT blocks This attempts to just fix the creation of VPT blocks, fixing up the iterating, which instructions are considered in the bundle, and making sure that we do not overrun the end of the block. Differential Revision: https://reviews.llvm.org/D67219 llvm-svn: 371064
2019-09-05 13:37:04 +00:00
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
[ARM] Masked load and store and predicate tests. NFC llvm-svn: 370325
2019-08-29 10:32:12 +00:00
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr
[MIR][ARM] MachineOperand comments This adds infrastructure to print and parse MIR MachineOperand comments. The motivation for the ARM backend is to print condition code names instead of magic constants that are difficult to read (for human beings). For example, instead of this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg t2Bcc %bb.4, 0, killed $cpsr we now print this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr This shows that MachineOperand comments are enclosed between /* and */. In this example, the EOR instruction is not conditionally executed (i.e. it is "always executed"), which is encoded by the 14 immediate machine operand. Thus, now this machine operand has /* CC::always */ as a comment. The 0 on the next conditional branch instruction represents the equal condition code, thus now this operand has /* CC:eq */ as a comment. As it is a comment, the MI lexer/parser completely ignores it. The benefit is that this keeps the change in the lexer extremely minimal and no target specific parsing needs to be done. The changes on the MIPrinter side are also minimal, as there is only one target hooks that is used to create the machine operand comments. Differential Revision: https://reviews.llvm.org/D74306
2020-02-24 14:19:21 +00:00
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
[ARM] Masked load and store and predicate tests. NFC llvm-svn: 370325
2019-08-29 10:32:12 +00:00
renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg
renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr
tBX_RET 14, $noreg, implicit $q0
...
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