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llvm-mirror/test/CodeGen/ARM/cmpxchg.mir

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[MIR][ARM] MachineOperand comments This adds infrastructure to print and parse MIR MachineOperand comments. The motivation for the ARM backend is to print condition code names instead of magic constants that are difficult to read (for human beings). For example, instead of this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg t2Bcc %bb.4, 0, killed $cpsr we now print this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr This shows that MachineOperand comments are enclosed between /* and */. In this example, the EOR instruction is not conditionally executed (i.e. it is "always executed"), which is encoded by the 14 immediate machine operand. Thus, now this machine operand has /* CC::always */ as a comment. The 0 on the next conditional branch instruction represents the equal condition code, thus now this operand has /* CC:eq */ as a comment. As it is a comment, the MI lexer/parser completely ignores it. The benefit is that this keeps the change in the lexer extremely minimal and no target specific parsing needs to be done. The changes on the MIPrinter side are also minimal, as there is only one target hooks that is used to create the machine operand comments. Differential Revision: https://reviews.llvm.org/D74306
2020-02-24 15:19:21 +01:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
ARMExpandPseudoInsts: Fix CMP_SWAP expansion adding a kill flag to a def llvm-svn: 346026
2018-11-02 19:22:15 +01:00
# RUN: llc -o - %s -mtriple=armv7-unknown-linux-gnu -verify-machineinstrs -run-pass=arm-pseudo | FileCheck %s
[ARM][atomicrmw] Fix CMP_SWAP_32 expand assert This assert is intended to ensure that the high registers are not selected when it is passed to one of the thumb UXT instructions. However it was triggering even for 32 bit where no UXT instruction is emitted. Fixes PR51313. Differential Revision: https://reviews.llvm.org/D107363 (cherry picked from commit 40650f27b5df95b2f96d25ea03976d8136804441)
2021-08-03 17:15:21 +02:00
# RUN: llc -o - %s -mtriple=thumbv7-unknown-linux-gnu -verify-machineinstrs -run-pass=arm-pseudo | FileCheck %s --check-prefix=THUMB
ARMExpandPseudoInsts: Fix CMP_SWAP expansion adding a kill flag to a def llvm-svn: 346026
2018-11-02 19:22:15 +01:00
---
name: func
tracksRegLiveness: true
body: |
bb.0:
liveins: $r0_r1, $r4_r5, $r3, $lr
[MIR][ARM] MachineOperand comments This adds infrastructure to print and parse MIR MachineOperand comments. The motivation for the ARM backend is to print condition code names instead of magic constants that are difficult to read (for human beings). For example, instead of this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg t2Bcc %bb.4, 0, killed $cpsr we now print this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr This shows that MachineOperand comments are enclosed between /* and */. In this example, the EOR instruction is not conditionally executed (i.e. it is "always executed"), which is encoded by the 14 immediate machine operand. Thus, now this machine operand has /* CC::always */ as a comment. The 0 on the next conditional branch instruction represents the equal condition code, thus now this operand has /* CC:eq */ as a comment. As it is a comment, the MI lexer/parser completely ignores it. The benefit is that this keeps the change in the lexer extremely minimal and no target specific parsing needs to be done. The changes on the MIPrinter side are also minimal, as there is only one target hooks that is used to create the machine operand comments. Differential Revision: https://reviews.llvm.org/D74306
2020-02-24 15:19:21 +01:00
; CHECK-LABEL: name: func
; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $r0_r1, $r4_r5, $r3, $lr
; CHECK: .1:
; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK: liveins: $r4_r5, $r3
; CHECK: $r0_r1 = LDREXD $r3, 14 /* CC::al */, $noreg
; CHECK: CMPrr killed $r0, $r4, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: CMPrr killed $r1, $r5, 0 /* CC::eq */, killed $cpsr, implicit-def $cpsr
; CHECK: Bcc %bb.3, 1 /* CC::ne */, killed $cpsr
; CHECK: .2:
; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000)
; CHECK: liveins: $r4_r5, $r3
; CHECK: early-clobber $r2 = STREXD $r4_r5, $r3, 14 /* CC::al */, $noreg
; CHECK: CMPri killed $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: Bcc %bb.1, 1 /* CC::ne */, killed $cpsr
; CHECK: .3:
[ARM][atomicrmw] Fix CMP_SWAP_32 expand assert This assert is intended to ensure that the high registers are not selected when it is passed to one of the thumb UXT instructions. However it was triggering even for 32 bit where no UXT instruction is emitted. Fixes PR51313. Differential Revision: https://reviews.llvm.org/D107363 (cherry picked from commit 40650f27b5df95b2f96d25ea03976d8136804441)
2021-08-03 17:15:21 +02:00
; THUMB-LABEL: name: func
; THUMB: successors: %bb.1(0x80000000)
; THUMB: liveins: $r0_r1, $r4_r5, $r3, $lr
; THUMB: .1:
; THUMB: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; THUMB: liveins: $r4, $r5, $r3
; THUMB: $r0, $r1 = t2LDREXD $r3, 14 /* CC::al */, $noreg
; THUMB: tCMPhir killed $r0, $r4, 14 /* CC::al */, $noreg, implicit-def $cpsr
; THUMB: tCMPhir killed $r1, $r5, 0 /* CC::eq */, killed $cpsr, implicit-def $cpsr
; THUMB: tBcc %bb.3, 1 /* CC::ne */, killed $cpsr
; THUMB: .2:
; THUMB: successors: %bb.1(0x40000000), %bb.3(0x40000000)
; THUMB: liveins: $r4, $r5, $r3
; THUMB: early-clobber $r2 = t2STREXD $r4, $r5, $r3, 14 /* CC::al */, $noreg
; THUMB: t2CMPri killed $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; THUMB: tBcc %bb.1, 1 /* CC::ne */, killed $cpsr
; THUMB: .3:
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
dead early-clobber renamable $r0_r1, dead early-clobber renamable $r2 = CMP_SWAP_64 killed renamable $r3, killed renamable $r4_r5, renamable $r4_r5 :: (volatile load store monotonic monotonic (s64))
ARMExpandPseudoInsts: Fix CMP_SWAP expansion adding a kill flag to a def llvm-svn: 346026
2018-11-02 19:22:15 +01:00
...
[ARM][atomicrmw] Fix CMP_SWAP_32 expand assert This assert is intended to ensure that the high registers are not selected when it is passed to one of the thumb UXT instructions. However it was triggering even for 32 bit where no UXT instruction is emitted. Fixes PR51313. Differential Revision: https://reviews.llvm.org/D107363 (cherry picked from commit 40650f27b5df95b2f96d25ea03976d8136804441)
2021-08-03 17:15:21 +02:00
---
name: func2
tracksRegLiveness: true
body: |
bb.0:
liveins: $r1, $r2, $r3, $r12, $lr
; CHECK-LABEL: name: func2
; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $r1, $r2, $r3, $r12, $lr
; CHECK: .1:
; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK: liveins: $lr, $r3, $r12
; CHECK: $r1 = LDREX $r3, 14 /* CC::al */, $noreg
; CHECK: CMPrr killed $r1, $r12, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: Bcc %bb.3, 1 /* CC::ne */, killed $cpsr
; CHECK: .2:
; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000)
; CHECK: liveins: $lr, $r3, $r12
; CHECK: early-clobber $r2 = STREX $lr, $r3, 14 /* CC::al */, $noreg
; CHECK: CMPri killed $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: Bcc %bb.1, 1 /* CC::ne */, killed $cpsr
; CHECK: .3:
; THUMB-LABEL: name: func2
; THUMB: successors: %bb.1(0x80000000)
; THUMB: liveins: $r1, $r2, $r3, $r12, $lr
; THUMB: .1:
; THUMB: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; THUMB: liveins: $lr, $r3, $r12
; THUMB: $r1 = t2LDREX $r3, 0, 14 /* CC::al */, $noreg
; THUMB: tCMPhir killed $r1, $r12, 14 /* CC::al */, $noreg, implicit-def $cpsr
; THUMB: tBcc %bb.3, 1 /* CC::ne */, killed $cpsr
; THUMB: .2:
; THUMB: successors: %bb.1(0x40000000), %bb.3(0x40000000)
; THUMB: liveins: $lr, $r3, $r12
; THUMB: early-clobber $r2 = t2STREX $lr, $r3, 0, 14 /* CC::al */, $noreg
; THUMB: t2CMPri killed $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; THUMB: tBcc %bb.1, 1 /* CC::ne */, killed $cpsr
; THUMB: .3:
dead early-clobber renamable $r1, dead early-clobber renamable $r2 = CMP_SWAP_32 killed renamable $r3, killed renamable $r12, killed renamable $lr
...
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